- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗10253 > CS181022-CQZ (Cirrus Logic Inc)IC COBRANET CS181022 144LQFP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | CS181022-CQZ |
| 寤犲晢锛� | Cirrus Logic Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 3/15闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC COBRANET CS181022 144LQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 60 |
| 绯诲垪锛� | CobraNet® |
| 椤炲瀷锛� | 闊抽牷铏曠悊鍣� |
| 鎳�(y墨ng)鐢細 | 缍�(w菐ng)绲�(lu貌) |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 144-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 144-LQFP锛�20x20锛� |
| 鍖呰锛� | 鎵樼洡 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 758 (CN2011-ZH PDF) |
| 閰嶇敤锛� | 598-1021-ND - MODULE COBRANET 4961 CM2 FB 598-1020-ND - MODULE COBRANET 1810 CM2 MT |
| 鍏跺畠鍚嶇ū锛� | 598-1026 |
CobraNet Hardware User鈥檚 Manual
Pinout and Signal Descriptions
DS651UM23
Copyright 2005 Cirrus Logic, Inc.
11
Version 2.3
4.1.2 CM-2 Connector Pinout
Table 1 lists the pinout for the four pinout connectors on the CM-2 board (J1-J4). The
interfaces for these signals are expanded following the table.
Table 2. CM-2 Pin Assignments
Conn.
Pin #
Pin Name
Conn.
Pin #
Pin Name
Conn.
Pin #
Pin Name
J1/J2
A1
UART_RXD
J1/J2
B8
GND
J3/J4
A15
DAI1_DATA3
J1/J2
A2
UART_TX_OE
J1/J2
B9
VCC_+3.3V
J3/J4
A16
RSVD3
J1/J2
A3
HACK
J1/J2
B10
GND
J3/J4
A17
WATCHDOG
J1/J2
A4
HR/W
J1/J2
B11
VCC_+3.3V
J3/J4
A18
RSVD4
J1/J2
A5
HDS
J1/J2
B12
GND
J3/J4
A19
AUX_POWER2
J1/J2
A6
HREQ
J1/J2
B13
VCC_+3.3V
J3/J4
A20
AUX_POWER0
J1/J2
A7
HEN
J1/J2
B14
GND
J3/J4
B1
GND
J1/J2
A8
HADDR0
J1/J2
B15
VCC_+3.3V
J3/J4
B2
VCC_+3.3V
J1/J2
A9
HADDR1
J1/J2
B16
GND
J3/J4
B3
GND
J1/J2
A10
HADDR2
J1/J2
B17
VCC_+3.3V
J3/J4
B4
VCC_+3.3V
J1/J2
A11
HDATA0
J1/J2
B18
RSVD1
J3/J4
B5
GND
J1/J2
A12
HDATA1
J1/J2
B19
GND
J3/J4
B6
VCC_+3.3V
J1/J2
A13
HDATA2
J1/J2
B20
VCC_+3.3V
J3/J4
B7
GND
J1/J2
A14
HDATA3
J3/J4
A1
RSVD2
J3/J4
B8
VCC_+3.3V
J1/J2
A15
HDATA4
J3/J4
A2
MUTE
J3/J4
B9
GND
J1/J2
A16
HDATA5
J3/J4
A3
FS1
J3/J4
B10
VCC_+3.3V
J1/J2
A17
HDATA6
J3/J4
A4
MCLK_OUT
J3/J4
B11
GND
J1/J2
A18
HRESET
J3/J4
A5
MCLK_IN
J3/J4
B12
VCC_+3.3V
J1/J2
A19
HDATA7
J3/J4
A6
REFCLK_IN
J3/J4
B13
GND
J1/J2
A20
HADDR3
J3/J4
A7
DAO1_SCLK/DAI1_SCLK
J3/J4
B14
VCC_+3.3V
J1/J2
B1
UART_TXD
J3/J4
A8
DAO1_DATA0
J3/J4
B15
GND
J1/J2
B2
GND
J3/J4
A9
DAO1_DATA1
J3/J4
B16
GND
J1/J2
B3
VCC_+3.3V
J3/J4
A10
DAO1_DATA2
J3/J4
B17
VCC_+5V
J1/J2
B4
GND
J3/J4
A11
DAO1_DATA3
J3/J4
B18
VCC_+5V
J1/J2
B5
VCC_+3.3V
J3/J4
A12
DAI1_DATA0
J3/J4
B19
AUX_POWER3
J1/J2
B6
GND
J3/J4
A13
DAI1_DATA1
J3/J4
B20
AUX_POWER1
J1/J2
B7
VCC_+3.3V
J3/J4
A14
DAI1_DATA2
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| AD1896AYRSZ | IC CONV SAMPLE RATE ASYNC 28SSOP |
| CS6422-CSZ | IC SPEAKERPHONE ENHANCED 20SOIC |
| CXC3106A14S7P | CONN PLUG 3POS STRGHT PIN |
| CS8421-CZZ | IC SAMPLE RATE CONVERTER 20TSSOP |
| CS8406-CZZ | IC XMITTER DGTL 192KHZ 28TSSOP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| CS181022-CQZ/A1 | 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:Digital Audio Networking Processor |
| CS181022-CQZR | 鍔熻兘鎻忚堪:闊抽牷 DSP IC CobraNet Audio Networking Processor RoHS:鍚� 鍒堕€犲晢:Texas Instruments 宸ヤ綔闆绘簮闆诲: 闆绘簮闆绘祦: 宸ヤ綔婧害鑼冨湇: 瀹夎棰�(f膿ng)鏍�: 灏佽 / 绠遍珨: 灏佽:Tube |
| CS1810XX | 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:New CobraNet Silicon Series Ideal for Digital Audio Networking Applications |
| CS1812-04 | 鍒堕€犲晢:CITRUSCOM 鍔熻兘鎻忚堪:EMI with ESD protection IC uDFN-8L |
| CS1812-08 | 鍒堕€犲晢:CITRUSCOM 鍔熻兘鎻忚堪: |
鐧�(f膩)甯冪穵鎬ラ噰璩硷紝3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
