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| 型號： | CPS1027-S |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 20/64頁 |
| 文件大小： | 870K |
| 代理商： | CPS1027-S |
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CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
Data Sheet
January 2002
Agere Systems Inc.
20
4 Architectural Information
(continued)
4.6 Serial I/O Configurations
4.6.1 Codec Data Transfer
When the codec is active, ACTIVE = 1 (see Table 7 on
page 26), it loads data into the
cdx(A/D)
and empties
data from the
cdx(D/A)
register (see Figure 3 on page
5) at the sampling frequency, f
S
(which is 8 kHz based
on a 1 MHz oversampling frequency). The codec data
transfers occur independent of the serial input/output
data transfers described below. The data is double
buffered, allowing the codec to transfer data to or from
the
cdx
while the serial I/O is shifting data into or out of
the shift registers (
isr
and
osr
). When the codec is set
to inactive, ACTIVE = 0, there are no codec data trans-
fers to the
cdx(A/D)
or from the
cdx(D/A)
.
The internal STATUS flag is set high when
cdx(A/D)
is
loaded and
cdx(D/A)
is emptied. Loading data from the
cdx(A/D)
into the output shift register (
osr
) or loading
data from the input shift register (
isr
) into the
cdx(D/A)
due to a serial I/O transaction, clears the internal STA-
TUS flag. The internal STATUS flag can be observed
on the data output (DO) pin in the passive mode and
causes data transfers in the active and multiprocessor
modes.
4.6.2 Codec Control Writes
The four control registers are written through the serial
port. The serial address (SADD) selects between con-
trol and data transfers. Bits 15 and 14 of the control
word being transferred select which control register,
cioc0
,
cioc1
,
cioc2
, or
cioc3
, is written (i.e.,
cioc0
:
Bit[15:14] = 00,
cioc1
: Bit[15:14] = 01, etc.).
4.6.3 Serial I/O Port Overview
The CSP1027 serial I/O unit is an asynchronous, full-
duplex, double-buffered channel operating at up to
20 Mbits/s that easily interfaces with other Agere fixed-
point DSPs (i.e., DSP16A and DSP1610/1616/1617/
1618) in a single or multiple DSP environment. Com-
mercially available codecs and time-division multi-
plexed (TDM) channels can be interfaced to the
CSP1027 device with little, if any, external logic.
The serial interface is a subset of the standard Agere
DSP serial I/O and is comprised of eight pins:
I
A single passive serial input/output clock (IOCK).
I
A combined input load, output load, and synchroni-
zation (SYNC).
I
Serial data input (DI).
I
Serial data output (DO).
I
Serial address (SADD).
I
Three serial mode select pins (SMODE[2:0]).
The CSP1027's serial I/O is different from the standard
Agere serial I/O in a number of ways:
I
The SMODE[1:0] pins configure the serial I/O port
into one of four possible ways: a passive SIO config-
uration, an active SIO configuration, and two multi-
processor SIO configurations.
I
A fixed most significant bit (MSB) first data format.
I
A fixed 16-bit data mode.
I
The serial address (SADD) is an input during the
passive and active SIO configurations to select
between data and control SIO transfers. It is
intended to be connected to the DSP’s SADD pin,
which is an output during passive and active SIO.
Note that the DSP's SADD output is inverted and is
composed of two 8-bit fields that are shifted out least
significant bit (LSB) first.
I
The multiprocessor mode time slots and serial
addresses are restricted to two sets, one of which is
selected based on the state of SMODE0.
I
The SMODE2 pin should always be tied low for the
serial I/O port to operate as described.
I
The frequency of the serial I/O interface clock input
IOCK (F
IOCK
) must be greater than the frequency of
the internal oversampling clock (F
IOCK
).
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