參數(shù)資料
型號： CPS1027-S
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁數(shù)： 2/64頁
文件大小： 870K
代理商： CPS1027-S
CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
Data Sheet
January 2002
Agere Systems Inc.
2
Table of Contents
Contents
Page
1
2
3
4
Features...................................................................................................................................................... 1
Description.................................................................................................................................................. 1
Pin Information ........................................................................................................................................... 3
Architectural Information ............................................................................................................................ 5
4.1
Overview........................................................................................................................................... 6
4.2
Description of Signal Paths............................................................................................................... 6
4.3
Programmable Features................................................................................................................. 13
4.4
Power-On Reset............................................................................................................................. 14
4.5
Clock Generation............................................................................................................................ 16
4.6
Serial I/O Configurations................................................................................................................. 20
Register Information.................................................................................................................................. 26
5.1
Codec I/O Control 0 (
cioc0
) Register............................................................................................. 26
5.2
Codec I/O Control 1 (
cioc1
) Register............................................................................................. 27
5.3
Codec I/O Control 2 (
cioc2
) Register............................................................................................. 28
5.4
Codec I/O Control 3 (
cioc3
) Register............................................................................................. 29
Signal Descriptions ................................................................................................................................... 30
6.1
Clock Interface................................................................................................................................ 30
6.2
Reset Interface ............................................................................................................................... 31
6.3
Serial I/O Interface.......................................................................................................................... 31
6.4
External Gain Control Interface ...................................................................................................... 32
6.5
Digital Power and Ground............................................................................................................... 32
6.6
Analog Interface.............................................................................................................................. 32
6.7
Analog Power and Ground ............................................................................................................. 32
Application Information ............................................................................................................................. 33
7.1
Analog Information.......................................................................................................................... 33
7.2
Power Supply Configuration........................................................................................................... 36
7.3
The Need for Fully Synchronous Operation ................................................................................... 36
7.4
Crystal Oscillator............................................................................................................................. 38
7.5
Programmable Clock Generation ................................................................................................... 45
Device Characteristics .............................................................................................................................. 47
8.1
Absolute Maximum Ratings............................................................................................................ 47
8.2
Handling Precautions...................................................................................................................... 47
8.3
Recommended Operating Conditions............................................................................................. 47
Electrical Characteristics and Requirements ............................................................................................ 48
9.1
Power Dissipation........................................................................................................................... 50
10 Analog Characteristics and Requirements................................................................................................ 51
10.1
Analog Input and Microphone Regulator........................................................................................ 51
10.2
Analog-to-Digital Path..................................................................................................................... 52
10.3
Digital-to-Analog Path..................................................................................................................... 53
10.4
Miscellaneous................................................................................................................................. 54
11 Timing Characteristics and Requirements................................................................................................ 55
11.1
Clock Generation............................................................................................................................ 56
11.2
Power-On Reset............................................................................................................................. 57
11.3
Reset .............................................................................................................................................. 58
11.4
Serial I/O Communication .............................................................................................................. 59
11.5
Serial Multiprocessor Communication............................................................................................ 61
12 Outline Diagrams ...................................................................................................................................... 62
12.1
44-Pin EIAJ Quad Flat Pack (QFP)................................................................................................ 62
12.2
48-Pin EIAJ Thin Quad Flat Pack (TQFP)...................................................................................... 63
5
6
7
8
9
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