參數(shù)資料
型號(hào)： COP8SEC5
廠商： National Semiconductor Corporation
英文描述： 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM
中文描述： 8位的CMOS基于ROM和OTP微控制器與4K的內(nèi)存和128字節(jié)伊拉姆
文件頁(yè)數(shù)： 9/47頁(yè)
文件大?。?/td> 491K
代理商： COP8SEC5
AC Electrical Characteristics
40C
≤
T
A
≤
+135C unless otherwise specified.
Parameter
Instruction Cycle Time (t
C
)
Crystal/Resonator, External
R/C Oscillator (Internal)
Frequency Variation (Note 22), (Note 21)
CKI Clock Duty Cycle (Note 22)
Rise Time (Note 22)
Fall Time (Note 22)
EERAM Write Cycle
Delay from Power-up to first EERAM Write
Cycle
Output Propagation Delay (Note 21)
Conditions
Min
Typ
Max
Units
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
fr = Max
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
1
3
DC
DC
±
20
55
12
8
15
65
μs
μs
%
%
ns
ns
ms
μs
45
7
R
L
= 2.2k, C
L
= 100
pF
t
PD1
, t
PD0
SO, SK
All Others
MICROWIRE Setup Time (t
UWS
) (Note 25)
MICROWIRE Hold Time (t
UWH
) (Note 25)
MICROWIRE Output Propagation Delay
(t
UPD
) (Note 25)
Input Pulse Width (Note 22)
Interrupt Input High Time
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
Reset Pulse Width
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
0.7
1.0
μs
μs
ns
ns
ns
20
56
220
1
1
1
1
1
t
C
t
C
t
C
t
C
μs
Note 16:
t
C
= Instruction cycle time.
Note 17:
Maximum rate of voltage change must be
<
0.5 V/ms.
Note 18:
Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180 out of phase with CKI, inputs connected to V
CC
and outputs driven low but not connected to a load.
Note 19:
The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
configuration, CKI is TRI-STATE. Measurement of I
DD
HALT is done with device neither sourcing nor sinking current; with L, G0, and G2–G5 programmed as low out-
puts and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V
CC
; clock monitor disabled. Parameter refers to HALT mode entered
via setting bit 7 of the G Port data register.
Note 20:
Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
>
V
and the pins will have sink current to V
when
biased at voltages
V
CC
(the pins do not have source current when biased at a voltage below V
CC
). The effective resistance to V
CC
is 750
(typical). These two
pins will not latch up. The voltage at the pins must be limited to
14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes
ESD transients.
Note 21:
The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 22:
Parameter characterized but not tested.
Note 23:
Rise times faster than the minimum specification may trigger an internal power-on-reset.
Note 24:
Exclusive of R and C variation.
Note 25:
MICROWIRE Setup and Hold Times and Propagation Delays are referenced to the appropriate edge of the MICROWIRE clock. See Figure 4 and the MI-
CROWIRE operation description.
DS100973-9
FIGURE 4. MICROWIRE/PLUS Timing
www.national.com
9
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