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| 型號： | COP8SEC5 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM |
| 中文描述： | 8位的CMOS基于ROM和OTP微控制器與4K的內(nèi)存和128字節(jié)伊拉姆 |
| 文件頁數(shù)： | 25/47頁 |
| 文件大小： | 491K |
| 代理商： | COP8SEC5 |
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8.0 Interrupts
(Continued)
8.3.1 VIS Execution
When the VIS instruction is executed it activates the arbitra-
tion logic. The arbitration logic generates an even number
between E0 and FE (E0, E2, E4, E6 etc...) depending on
which active interrupt has the highest arbitration ranking at
the time of the 1st cycle of VIS is executed. For example, if
the software trap interrupt is active, FE is generated. If the
external interrupt is active and the software trap interrupt is
not, then FAis generated and so forth. If the only active inter-
rupt is software trap, than E0 is generated. This number re-
places the lower byte of the PC. The upper byte of the PC re-
mains unchanged. The new PC is therefore pointing to the
vector of the active interrupt with the highest arbitration rank-
ing. This vector is read from program memory and placed
into the PC which is now pointed to the 1st instruction of the
service routine of the active interrupt with the highest arbitra-
tion ranking.
Figure 19 illustrates the different steps performed by the VIS
instruction. Figure 20 shows a flowchart for the VIS instruc-
tion.
The non-maskable interrupt pending flag is cleared by the
RPND (Reset Non-Maskable Pending Bit) instruction (under
certain conditions) and upon RESET.
DS100973-29
FIGURE 19. VIS Operation
www.national.com
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