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參數(shù)資料
| 型號： | COP8SEC5 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM |
| 中文描述： | 8位的CMOS基于ROM和OTP微控制器與4K的內(nèi)存和128字節(jié)伊拉姆 |
| 文件頁數(shù)： | 2/47頁 |
| 文件大?。?/td> | 491K |
| 代理商： | COP8SEC5 |
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Block Diagram
1.0 Device Description
1.1 ARCHITECTURE
The COP8 family is based on a modified Harvard architec-
ture, which allows data tables to be accessed directly from
program memory. This is very important with modern
microcontroller-based applications, since program memory
is usually ROM or EPROM, while data memory is usually
RAM. Consequently data tables need to be contained in
non-volatile memory, so they are not lost when the microcon-
troller is powered down. Non-memory for the storage of data
variables is provided by the EERAM in the COP8SEC5 and
COP8SER7. In a Harvard architecture, instruction fetch and
memory data transfers can be overlapped with a two stage
pipeline, which allows the next instruction to be fetched from
program memory while the current instruction is being ex-
ecuted using data memory. This is not possible with a Von
Neumann single-address bus architecture.
The COP8 family supports a software stack scheme that al-
lows the user to incorporate many subroutine calls. This ca-
pability is important when using High Level Languages. With
a hardware stack, the user is limited to a small fixed number
of stack levels.
1.2 INSTRUCTION SET
In today’s 8-bit microcontroller application arena cost/
performance, flexibility and time to market are several of the
key issues that system designers face in attempting to build
well-engineered products that compete in the marketplace.
Many of these issues can be addressed through the manner
in which a microcontroller’s instruction set handles process-
ing tasks. And that’s why the COP8 family offers a unique
and code-efficient instruction set— one that provides the
flexibility, functionality, reduced costs and faster time to mar-
ket that today’s microcontroller based products require.
Code efficiency is important because it enables designers to
pack more on-chip functionality into less program memory
space (ROM/OTP). Selecting a microcontroller with less pro-
gram memory size translates into lower system costs, and
the added security of knowing that more code can be packed
into the available program memory space.
1.2.1 Key Instruction Set Features
The COP8 family incorporates a unique combination of in-
struction set features, which provide designers with optimum
code efficiency and program memory utilization.
Single Byte/Single Cycle Code Execution
The efficiency is due to the fact that the majority of instruc-
tions are of the single byte variety, resulting in minimum pro-
gram space. Because compact code does not occupy a sub-
stantial amount of program memory space, designers can
integrate additional features and functionality into the micro-
controller program memory space. Also, the majority instruc-
tions executed by the device are single cycle, resulting in
minimum program execution time. In fact, 77% of the instruc-
tions are single byte single cycle, providing greater code and
I/O efficiency, and faster code execution.
1.2.2 Many Single-Byte, Multifunction Instructions
The COP8 instruction set utilizes many single-byte, multi-
function instructions. This enables a single instruction to ac-
complish multiple functions, such as DRSZ, DCOR, JID, LD
(Load) and X (Exchange) instructions with post-incrementing
and post-decrementing, to name just a few examples. In
many cases, the instruction set can simultaneously execute
as many as three functions with the same single-byte in-
struction.
JID:
(Jump Indirect); Single byte instruction; decodes exter-
nal events and jumps to corresponding service routines
(analogous to “DO CASE” statements in higher level lan-
guages).
LAID:
(Load Accumulator-Indirect); Single byte look up table
instruction provides efficient data path from the program
DS100973-44
FIGURE 1. Block Diagram
www.national.com
2
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