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參數(shù)資料
| 型號： | COP8SDR9LVA8 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout |
| 中文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 62/80頁 |
| 文件大?。?/td> | 972K |
| 代理商： | COP8SDR9LVA8 |
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18.0 Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address
S/ADD REG
0000 to 006F
0070 to 007F
Contents
On-Chip RAM bytes (112 bytes)
Unused RAM Address Space (Reads
As All Ones)
Unused RAM Address Space (Reads
Undefined Data)
Port E Data Register
Port E Configuration Register
Port E Input Pins (Read Only)
Reserved for Port E
Port F Data Register
Port F Configuration Register
Port F Input Pins (Read Only)
Reserved for Port F
Reserved
Port A Data Register
Port A Configuration Register
Port A Input Pins (Read Only)
Reserved for Port A
Port B Data Register
Port B Configuration Register
Port B Input Pins (Read Only)
Reserved for Port B
ISP Address Register Low Byte
(ISPADLO)
ISP Address Register High Byte
(ISPADHI)
ISP Read Data Register (ISPRD)
ISP Write Data Register (ISPWR)
Reserved
Reserved
Reserved
High Speed Timers Control Register
(HSTCR)
Timer T3 Lower Byte
Timer T3 Upper Byte
Timer T3 Autoload Register T3RA
Lower Byte
Timer T3 Autoload Register T3RA
Upper Byte
Timer T3 Autoload Register T3RB
Lower Byte
Timer T3 Autoload Register T3RB
Upper Byte
Timer T3 Control Register
Reserved
USART Transmit Buffer (TBUF)
USART Receive Buffer (RBUF)
xx80 to xx90
xx90
xx91
xx92
xx93
xx94
xx95
xx96
xx97
xx98 to xx9F
xxA0
xxA1
xxA2
xxA3
xxA4
xxA5
xxA6
xxA7
xxA8
xxA9
xxAA
xxAB
xxAC
xxAD
xxAE
xxAF
xxB0
xxB1
xxB2
xxB3
xxB4
xxB5
xxB6
xxB7
xxB8
xxB9
Address
S/ADD REG
xxBA
Contents
USART Control and Status Register
(ENU)
USART Receive Control and Status
Register (ENUR)
USART Interrupt and Clock Source
Register (ENUI)
USART Baud Register (BAUD)
USART Prescale Select Register
(PSR)
Reserved for USART
Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA
Lower Byte
Timer T2 Autoload Register T2RA
Upper Byte
Timer T2 Autoload Register T2RB
Lower Byte
Timer T2 Autoload Register T2RB
Upper Byte
Timer T2 Control Register
WATCHDOG Service Register
(Reg:WDSVR)
MIWU Edge Select Register
(Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register
(Reg:WKPND)
Reserved
Idle Timer Control Register (ITMR)
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Reserved
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D
Reserved for Port D
Reserved
Flash Memory Write Timing Register
(PGMTIM)
ISP Key Register (ISPKEY)
Reserved
Timer T1 Autoload Register T1RB
Lower Byte
xxBB
xxBC
xxBD
xxBE
xxBF
xxC0
xxC1
xxC2
xxC3
xxC4
xxC5
xxC6
xxC7
xxC8
xxC9
xxCA
xxCB to xxCE
xxCF
xxD0
xxD1
xxD2
xxD3
xxD4
xxD5
xxD6
xxD7
xxD8
xxD9
xxDA
xxDB
xxDC
xxDD to xxDF
xxE0
xxE1
xxE2
xxE3 to xxE5
xxE6
C
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