參數(shù)資料
型號(hào): COP8CBR9LVA8
廠商: National Semiconductor
文件頁(yè)數(shù): 73/111頁(yè)
文件大?。?/td> 0K
描述: IC MCU EEPROM 8BIT 32K 68PLCC
標(biāo)準(zhǔn)包裝: 18
系列: COP8™ 8C
核心處理器: COP8
芯體尺寸: 8-位
速度: 20MHz
連通性: Microwire/Plus(SPI),UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 59
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-LCC(J 形引線)
包裝: 管件
其它名稱(chēng): *COP8CBR9LVA8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Figure 5-17. Framing Formats
5.13.6 USART INTERRUPTS
The USART is capable of generating interrupts. Interrupts are generated on Receive Buffer Full and
Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two bytes of program memory
space are reserved for each interrupt vector. The two vectors are located at addresses 0xEC to 0xEF Hex
in the program memory space. The interrupts can be individually enabled or disabled using Enable
Transmit Interrupt (ETI) and Enable Receive Interrupt (ERI) bits in the ENUI register.
The interrupt from the Transmitter is set pending, and remains pending, as long as both the TBMT and
ETI bits are set. To remove this interrupt, software must either clear the ETI bit or write to the TBUF
register (thus clearing the TBMT bit).
The interrupt from the receiver is set pending, and remains pending, as long as both the RBFL and ERI
bits are set. To remove this interrupt, software must either clear the ERI bit or read from the RBUF register
(thus clearing the RBFL bit).
64
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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