參數(shù)資料
型號: COP8CBR9LVA8
廠商: National Semiconductor
文件頁數(shù): 38/111頁
文件大?。?/td> 0K
描述: IC MCU EEPROM 8BIT 32K 68PLCC
標準包裝: 18
系列: COP8™ 8C
核心處理器: COP8
芯體尺寸: 8-位
速度: 20MHz
連通性: Microwire/Plus(SPI),UART/USART
外圍設(shè)備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 59
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-LCC(J 形引線)
包裝: 管件
其它名稱: *COP8CBR9LVA8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
BUSY
MICROWIRE/PLUS busy shifting flag
EXEN
Enable external interrupt
GIE
Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that affect the Carry flag. The SC (Set Carry)
and R/C (Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC
and R/C instructions, ADC, SUBC, RRC and RLC instructions affect the Carry and Half Carry flags.
5.9.3
ICNTRL Register (Address X
00E8)
Unused
LPEN
T0PND
T0EN
WPND
WEN
T1PNDB
T1ENB
Bit 7
Bit 0
The ICNTRL register contains the following bits:
LPEN
L Port Interrupt Enable (Multi-Input Wake-up/Interrupt)
T0PND
Timer T0 Interrupt pending
T0EN
Timer T0 Interrupt Enable (Bit 12 toggle)
μWPND
MICROWIRE/PLUS interrupt pending
μWEN
Enable MICROWIRE/PLUS interrupt
T1PNDB
Timer T1 Interrupt Pending Flag for T1B capture edge
T1ENB
Timer T1 Interrupt Enable for T1B Input capture edge
5.9.4
T2CNTRL Register (Address X
00C6)
T2C3
T2C2
T2C1
T2C0
T2PNDA
T2ENA
T2PNDB
T2ENB
Bit 7
Bit 0
The T2CNTRL register contains the following bits:
T2C3
Timer T2 mode control bit
T2C2
Timer T2 mode control bit
T2C1
Timer T2 mode control bit
T2C0
Timer T2 Start/Stop control in timer modes 1 and 2, Timer T2 Underflow Interrupt Pending
Flag in timer mode 3
T2PNDA
Timer T2 Interrupt Pending Flag (Autoreload RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3)
T2ENA
Timer T2 Interrupt Enable for Timer Underflow or T2A Input capture edge
T2PNDB
Timer T2 Interrupt Pending Flag for T2B capture edge
T2ENB
Timer T2 Interrupt Enable for T2B Input capture edge
5.9.5
T3CNTRL Register (Address X
00B6)
T3C3
T3C2
T3C1
T3C0
T3PNDA
T3ENA
T3PNDB
T3ENB
Bit 7
Bit 0
32
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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