參數(shù)資料
型號: CO561AD-S
英文描述: Ichip Internet Controller(Internet網(wǎng)絡(luò)控制器)
中文描述: Ichip互聯(lián)網(wǎng)控制器(互聯(lián)網(wǎng)網(wǎng)絡(luò)控制器)
文件頁數(shù): 34/39頁
文件大?。?/td> 1576K
代理商: CO561AD-S
PCB Design and Layout Considerations
iChip Plus CO561AD-D Datasheet
8-2
signals together, they should be separated by neutral signals. For the iChip LAN
version, void power/ground plane as well as other digital signals between the
CS8900A and the RJ45 module.
5. All power and ground traces should be at least 0.05 in. wide.
6. 0.1 UF ceramic capacitors should be placed as close as possible to the power pins.
When internal power plane is used, the traces connecting between the power pins
of the components and the vias should be kept short and to have bypass capacitor
between the via and the pin.
7. In a modem design, TIP and RING signal traces are to be no closer than 0.062"
from any other traces for U.S. applications. TIP and RING signal traces are to be
no closer than 2.5mm (0.1”) from any other traces for European applications.
2.5mm spacing must be used if the host board is to support both U.S. and
European Socket Modems. In multi layer design, power and ground planes should
be cleared underneath the traces, which belong to the primary (TIP and RING)
circuit. For an Ethernet design, route differential signals (RXD, TXD) close
together as pairs. Try to avoid vias.
8. In a modem design, if the SocketModem is mounted flush with the host PCB, the
host PCB should be clear of all traces directly underneath the SocketModem
oscillator section. It is strongly suggested that the SocketModem be mounted at
least 0.130 inch above the host board.
8.2.1 Electromagnetic Interference (EMI) Considerations
In a modem design, the following guidelines are offered to specifically help minimize
EMI generation. Some of these guidelines are the same as, or similar to, the general
guidelines but are mentioned again to reinforce their importance. In order to minimize the
contribution of the SocketModem-based design to EMI, the designer must understand the
major sources of EMI and how to reduce them to acceptable levels.
1. Keep traces carrying high frequency signals as short as possible.
2. Decouple power from ground with decoupling capacitors as close to the active
components’ power pins as possible.
3. Eliminate ground loops, which are unexpected current return paths to the power
source and ground.
4. Decouple the telephone line cables at the telephone line jacks. Typically, use
common mode chokes and shunt capacitors. Methods to decouple telephone lines
are similar to decoupling power lines, however, telephone line decoupling may be
more difficult and deserves additional attention. A commonly used design aid is to
place footprints for these components and populate as necessary during
performance/EMI testing and certification.
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