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參數(shù)資料
| 型號： | CO561AD-S |
| 英文描述： | Ichip Internet Controller(Internet網(wǎng)絡(luò)控制器) |
| 中文描述： | Ichip互聯(lián)網(wǎng)控制器（互聯(lián)網(wǎng)網(wǎng)絡(luò)控制器） |
| 文件頁數(shù)： | 17/39頁 |
| 文件大?。?/td> | 1576K |
| 代理商： | CO561AD-S |
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Pin Descriptions
iChip Plus CO561AD-D Datasheet 5-2
5.2 iChip Plus Pin Functional Descriptions
5.2.1 Local Bus Signals
A19–A0
Address Bus (output, three-state, synchronous)
These pins supply non-multiplexed memory or I/O addresses to the system one half of a
CLKO period earlier than the multiplexed address and data bus AD15–AD0. During a
bus hold or reset condition, the address bus is in a high-impedance state.
AD15–AD0
Address and Data Bus (input/output, three-state, synchronous, level-sensitive)
AD15–AD0
—These time-multiplexed pins supply memory or I/O addresses and data to
the system. This bus can supply an address to the system during the first period of a bus
cycle. It supplies data to the system during the remaining periods of that cycle. When
~WR is deasserted, these pins are three-stated.
ALE
Address Latch Enable (output, synchronous)
This pin indicates to the system that an address appears on the address and data bus
(AD15–AD0). The address is guaranteed to be valid on the trailing edge of ALE. This pin
is not three-stated during a bus hold or reset.
~
BHE
Bus High Enable (three-state, output, synchronous)
During a memory access, this pin and the least-significant address bit (A0) indicate to the
system, which bytes of the data bus (upper, lower, or both) participate in a bus cycle. The
~BHE and A0 pins are encoded as shown in the table below.
~BHE
A0
0
0
1
0
0
1
1
1
Type of bus cycle
Word Transfer
Even Byte Transfer
Odd Byte Transfer
N/A
Table
5-1 Data Byte Encoding
BHE floats during reset.
CLKO
Clock Output.
This pin Supplies the internal clock to the system. CLKO remains active during RESET.
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