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參數(shù)資料
| 型號： | CO561AD-S |
| 英文描述： | Ichip Internet Controller(Internet網(wǎng)絡(luò)控制器) |
| 中文描述： | Ichip互聯(lián)網(wǎng)控制器（互聯(lián)網(wǎng)網(wǎng)絡(luò)控制器） |
| 文件頁數(shù)： | 32/39頁 |
| 文件大?。?/td> | 1576K |
| 代理商： | CO561AD-S |
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iChip Plus Designs
iChip Plus CO561AD-D Datasheet
7-1
7.4 PLD Equations for Embedded Dual
------------------------------------------------------------------
-- File name:
dualref.vhd
-- Designed by:
Leonid Epstein
-- Purpose:
Dual board Control Logic.
-- The board memory map:
-- 0x00000 - 0x1ffff - system SRAM
-- 0x20000 - 0x23fff - LAN IO space (16KB)
--
(default IO 0x300 so the first access s.b. to 0x20300)
-- 0x3C000 - 0x3ffff - LAN memory space (16KB)
-- 0x80000 - 0xfffff - System FLASH
------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity imdlnref is
port (
a : in std_logic_vector(19 downto 14);
wr_n : in std_logic;
rd_n : in std_logic;
iowr_n : out std_logic;
iord_n : out std_logic;
);
attribute loc : string ;
attribute loc of wr_n : signal is "P2" ;
attribute loc of rd_n : signal is "P3" ;
attribute loc of a14 : signal is "P4" ;
attribute loc of a15 : signal is "P5" ;
attribute loc of a16 : signal is "P6" ;
attribute loc of a17 : signal is "P7" ;
attribute loc of a18 : signal is "P8" ;
attribute loc of a19 : signal is "P9" ;
attribute loc of iowr_n : signal is "P15" ;
attribute loc of iord_n : signal is "P16" ;
end imdlnref;
architecture behavioral of dualref is
signal io_access: std_logic;
begin
io_access <= '1' when a(19 downto 14) = "001000"
else '0'; -- 0x20000 - 0x23FFF ;
iowr_n <= wr_n when io_access = '1' or dma_access = '1' else '1';
iord_n <= rd_n when io_access = '1' or dma_access = '1' else '1';
end behavioral;
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