參數(shù)資料
型號: CO561AD-D
英文描述: Ichip Internet Controller(Internet網(wǎng)絡控制器)
中文描述: Ichip互聯(lián)網(wǎng)控制器(互聯(lián)網(wǎng)網(wǎng)絡控制器)
文件頁數(shù): 22/52頁
文件大小: 1835K
代理商: CO561AD-D
Pin Descriptions
iChip & iChip LAN Datasheet 5-5
~WR
Write Strobe (output, synchronous)
This pin indicates to the system that the data on the bus is to be written to a memory or
I/O device. ~WR floats during reset condition.
X1
Crystal Input (input)
This pin and the X2 pin provide connections for a fundamental mode or third-overtone,
parallel-resonant crystal used by the internal oscillator circuit. To provide the iChip with
an external clock source, connect the source to the X1 pin and leave the X2 pin
unconnected.
X2
Crystal Output (output)
This pin and the X1 pin provide connections for a fundamental mode or third-overtone,
parallel-resonant crystal used by the internal oscillator circuit. To provide the iChip with
an external clock source, leave the X2 pin unconnected and connect the source to the X1
pin.
Selecting a Crystal
Figure
5-3 Selecting a Crystal
The characteristics of the built-in inverting amplifier set limits on the following
parameters for crystals:
Crystal first overtone frequency .................. 18.432 MHz
ESR (Equivalent Series Resistance) ............ 40
max
Drive Level ............................................….. 1 mW max
The recommended range of values for C 1 and C 2 are as follows:
C 1 ............................................................... 15 pF ± 20%
C 2 ............................................................... 22 pF ± 20%
The specific values for C1 and C2 must be determined by the designer and are dependent
on the characteristics of the chosen crystal and board design.
GND
Ground
Ground pins connect the iChip to the system ground.
X1
X2
C1
C2
Crystal
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