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參數(shù)資料
| 型號： | CO561AD-D |
| 英文描述： | Ichip Internet Controller(Internet網絡控制器) |
| 中文描述： | Ichip互聯(lián)網控制器（互聯(lián)網網絡控制器） |
| 文件頁數(shù)： | 21/52頁 |
| 文件大?。?/td> | 1835K |
| 代理商： | CO561AD-D |
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Pin Descriptions
iChip & iChip LAN Datasheet 5-4
~UCS
Upper Chip Select (output, synchronous)
This pin indicates to the system that that a memory access is in progress to the Flash
memory.
Normally this pin should be Open.
HOLD
Bus Hold Request (input, synchronous, level sensitive)
This pin indicates to the iChip that an external bus master needs control of the local bus .
Normally this pin should connect to GND.
HLDA
Bus Hold Acknowledge (output , synchronous, level sensitive)
This pin asserted High to indicate to an external bus master that the iChip has release
control of local bus. Normally this pin should be Open.
~LCS
Low memory Ram Chip Select (output, synchronous)
This pin indicates to the system that that a memory access is in progress to the Static Ram
memory. Normally this pin should be Open.
~RD
Read Strobe (output, synchronous, three-state)
This pin indicates to the system that the iChip is performing a memory or I/O read cycle.
~RD is guaranteed to not be asserted before the address and data bus is floated during the
address-to-data transition. ~RD floats during a bus hold condition.
~
RES
Reset (input, asynchronous, level-sensitive)
This pin requires the iChip to perform a reset.
When ~RES is asserted, the iChip immediately terminates its present activity and clears
its internal logic.
~RES must be held Low for at least 1 ms.
~RES can be asserted asynchronously to CLKO because ~RES is synchronized
internally. For proper initialization, VCC must be within specifications, and CLKO must
be stable for more than four CLKO periods during which RES is asserted. The iChip
begins fetching instructions approximately 6.5 CLKO periods after ~RES is de-asserted.
This input is provided with a Schmidt trigger to facilitate power-on RES generation via
an RC network.
URTINT
Uart Interrupt (input , asynchronous)
This pin for debugging only . It must be pull up to Vcc with resistor of 4.7K.
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PDF描述 |
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| CO561AD-S | Ichip Internet Controller(Internet網絡控制器) |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CO561AD-D/20PC-3 | 制造商:Connect One 功能描述:COMMUNICATION ICHIP PLUS INTERNET CONTROLLER 68PLCC |
| CO561AD-D/20PC-5 | 制造商:Connect One 功能描述:COMMUNICATION ICHIP PLUS INTERNET CONTROLLER 68PLCC |
| CO561AD-L/20PC-3 | 制造商:Connect One 功能描述:COMMUNICATION ICHIP PLUS INTERNET CONTROLLER 68PLCC |
| CO561AD-L/20PC-3G | 制造商:Connect One 功能描述:CO561AD-L SERIAL LAN VERSION, |
| CO561AD-L/20PC-5 | 制造商:Connect One 功能描述:Internet Controller, Ichip LAN Evaluation Platform, Plcc-68 Form FACtor, 5 V |
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