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參數(shù)資料
| 型號(hào)： | CM3121-02SH |
| 廠商： | California Micro Devices Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Dual Linear Voltage Regulator for DDR-I and DDR-II Memory |
| 中文描述： | 雙線性穩(wěn)壓器，用于DDR I和DDR - II內(nèi)存 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 219K |
| 代理商： | CM3121-02SH |
2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
11/12/04
CM3121
PRELIMINARY
Functional Description
The CM3121 provides power for DDR-I/DDR-II memo-
ries from two voltage regulators on-chip. There is an
over-temperature thermal shutdown if any of the regu-
lators overheat. Each regulator also has reverse cur-
rent protection in the event of any being shut down.
The V
DDQ
linear regulator can provide 2.5V/1.8V for
DDR-I/-II memory at up to 1.5A. An external feedback
resistor divider R1 and R2, when connected to the
SENSE_V
DDQ
pin, enables selection of V
DDQ
output
voltages from 2.2V to 2.8V for use with DDR-I memo-
ries requiring other than 2.5V for V
DDQ
(see
Figure 5
).
In this mode, the voltage on VDDQ is detemined as fol-
lows:
V
DDQ
= 1.25V x
When SENSE_V
DDQ
is connected to GND or left open,
V
DDQ
is fixed at 2.50V (and V
TT
at 1.25V). For DDR-II
operation, V
DDQ
can be set from 1.7V to 1.9V. The V
TT
regulator is a linear source-sink regulator powered
from the V
DDQ
output that supplies the V
TT
supply
required by DDR-I memory termination resistors. This
regulator sinks or sources up to 0.5A. The V
TT
output
voltage accurately tracks V
DDQ
/2 to 1%. When there is
no V
CC
provided, V
TT
is powered down and its output
is 0V. This regulator has overload current limiting of
0.6A minimum.
The EN_DDR pin when set active low enables the
CM3121 to operate in normal mode with V
DDQ
and V
TT
active. When EN_DDR is high, the CM3121 is disabled
and both V
DDQ
and V
TT
are set to 0V.
The FAULT output is normally at logic high but when
an overcurrent occurs on either V
DDQ
or V
TT
outputs,
FAULT goes active low, and remains low as long as
the overcurrent fault persists. Also if the chip goes into
thermal overload, or the input voltage V
CC
drops suffi-
ciently that the chip goes into Under Voltage Lock-Out
mode (UVLO), FAULT goes active low, and remains
low as long as the condition persists.
(R1+R2)
R2
----------------------
PIN DESCRIPTIONS
LEAD
NAME
DESCRIPTION
1
V
CC
V
DDQ
V
TT
GND
EN_DDR
SENSE_V
TT
FAULT
SENSE_V
DDQ
GND
Input supply.
2
V
DDQ
output.
V
TT
output for termination resistors or V
REF
Ground reference.
Enable DDR power. Active low input.
Sense input for V
TT
rail adjustment.
Overcurrent Fault / UVLO indication, active low output.
Sense input for V
DDQ
rail adjustment.
Tied to ground reference.
3
4
5
6
7
8
PAD
PACKAGE / PINOUT DIAGRAM
Note: This drawing is not to scale.
8-Lead PSOP
1
2
3
4
8
7
6
5
V
CC
V
DDQ
V
TT
GND
SENSE_V
DDQ
FAULT
SENSE_V
TT
EN_DDR
TOP VIEW
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