參數(shù)資料
型號: CM3121-02SB
廠商: California Micro Devices Corporation
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Dual Linear Voltage Regulator for DDR-I and DDR-II Memory
中文描述: 雙線性穩(wěn)壓器,用于DDR I和DDR - II內(nèi)存
文件頁數(shù): 5/11頁
文件大?。?/td> 219K
代理商: CM3121-02SB
2004 California Micro Devices Corp. All rights reserved.
11/12/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
5
CM3121
PRELIMINARY
Note 1: All parameters specified at T
A
= -40°C to +85°C unless otherwise noted.
Note 2: Note that the I
DDQ
current specified is the load current output from the V
DDQ
pin. V
DDQ
also supplies current internally to the
V
TT
regulator when it is sourcing current. The maximum source current can be up to 0.5A. So the maximum total current
from the V
DDQ
regulator is the external V
DDQ
current I
DDQ
added to the maximum V
TT
sourcing current I
TT
. All load currents
are specified as such, but the V
DDQ
current limit is specified at a current just above the total maximum current.
DDR-II Specifications
V
TT
Regulator Parameters
V
TT
Output Voltage Range
V
TT REF
Output Voltage Range
V
TT LD
Load Regulation
V
DDQ
= 2.5V, I
TT
= 0.01A,
V
DDQ
= 2.500V, I
TT
= 0.01A
T
A
= 25°C, V
DDQ
= 2.5V,
0.01A
I
TT
±
0.5A
T
A
= 25°C, I
TT
= 0.01A,
2.8V
V
CC
3.6V, Note 2
BW = 10Hz - 100kHz, C
TT
= 10
μ
F
1.20
1.25
1.30
V
1.225
1.250
1.275
V
-1.0
-
1.0
%
V
TT LINE
Line Regulation
-1.0
-
1.0
%
e
N TT
I
TT LIM
I
TT SC
Output Noise Voltage
51
μ
Vrms
Current Limit
0.6
0.8
A
Short Circuit Current
V
TT
< 0.3V
0.3
A
ELECTRICAL OPERATING CHARACTERISTICS (CONT’D)
(SEE NOTE1)
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
General Parameters
T
OVER
T
HYST
I
CCN
Shutdown Junction Temperature
-
150
-
°C
Junction Temp Hysterisis
IC in shutdown
-
25
-
°C
Normal Mode V
CC
Supply
Current
EN_DDR = logic "0",
700
1100
μ
A
I
CCQ
Shutdown Mode V
CC
Supply
Current
EN_DDR = logic "1",
V
DDQ
= 0V, V
TT
= 0V
V
CC
=3.3V
V
CC
=3.3V
I
DDQ
= 10mA
2
10
μ
A
V
IH
V
IL
UVLO
EN_DDR Input High Threshold
2.0
V
EN_DDR Input Low Threshold
0.4
V
Under Voltage Lock-Out
1.8
V
t
RISE
V
DDQ
Rise TIme
V
CC
= 3.3V, C
DDQ
= 10
μ
F
0.5
ms
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