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參數(shù)資料
| 型號： | CLR75000 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 75K |
| 代理商： | CLR75000 |
CLR70000
3
CELL LIBRARIES
Core Cells
The CLR70000 array family employs the extensive CLA70000 core cell libraries developed from a broad range of ASIC
experience over more than 15 years. Gate level and SSI functions are included in the MICROCELL Library, for implementation
of ‘glue’ logic and customer specific macros. To increase design productivity, the MACROCELL Library contains optimised SSI
macro functions similar to standard TTL and CMOS logic families. A higher level of cells, particularly suitable for digital signal
processing functions are to be found in the DSP MACROCELL Library. Memory cells (RAM and ROM) are individually generated
within the PARACELL Library. To aid in testing of devices the BIST Library contains JTAG/IEEE-1149.1 elements facilitating
Built-In-Self-Test methods such as scan path and signature analysis. More detailed information on all these libraries can be found
in the CLA70000 datasheet, the CLA70000 design manual and the BIST application guide.
PERIPHERAL CELLS
INTERMEDIATE BUFFER CELLS
Cell
NPIBSK1
NPIBSK2
NPIBSK3
NPIBTRID
NPIBTRID1
NPIBTRID2
NPIBTRID3
NPIB2BD
NPDRV3
NPDRV6
Cell
NPIBCMOS1
NPIBCMOS2
NPIBTTL1
NPIBBTL2
NPIBST1
NPIBST2
NPIBGATE
NPIBCLKB
NPIBDF
NPIBDFA
Description
CMOS input buffer + large 2 input NAND gate
CMOS input buffer + data latch
TTL input buffer + large 2 input NAND gate
TTL input buffer + data latch
Input Schmitt buffer with CMOS switching levels
Input Schmitt buffer with 2V switching levels
NAND2/NOR2 gates
Large clock driver
Master-slave D type flip flop
Master-slave D type flip flop
Description
Driver with slewed outputs
Driver with slewed outputs
Driver with slewed outputs
Tri-state driver
Tri-state driver with slewed outputs + 2 inverters
Tri-state driver with slewed outputs + 2 inverters
Tri-state driver with slewed outputs + 2 inverters
Dual high powered inverters
Clock driver
Clock driver
OUTPUT CELLS
Cell
NPOP1
NPOP2
NPOP3
NPOP6
NPOP12
NPOP5B
NPOP11B
NPOPT1
NPOPT2
NPOPT3
NPOPT6
NPOPT12
NPOP4TB
NPOP10TB
Description
Smallest drive output cell
Small drive output cell
Standard drive output cell
Medium drive output cell
Large drive output cell
Standard drive non-inverting output cell
Large drive non-inverting output cell
Smallest drive tri-state output cell
Small drive tri-state output cell
Standard drive tri-state output cell
Medium drive tri-state output cell
Large drive tri-state output cell
Standard drive non-inverting tri-state output cell
Large drive non-inverting tri-state output cell
Cell
NPOPOD1
NPOPOD2
NPOPOD3
NPOPOD6
NPOPOD12
NPOPOD5B
NPOPOD11B
NPOPOS1
NPOPOS2
NPOPOS3
NPOPOS6
NPOPOS12
NPOPOS5B
NPOPOS11B
Description
Smallest drive open-drain output cell
Small drive open-drain output cell
Standard drive open-drain output cell
Medium drive open-drain output cell
Large drive open-drain output cell
Standard drive non-inverting open-drain output cell
Large drive non-inverting open-drain output cell
Smallest drive open-source output cell
Small drive open-source output cell
Standard drive open-source output cell
Medium drive open-source output cell
Large drive open-source output cell
Standard drive non-inverting open-source output cell
Large drive non-inverting open-source output cell
INPUT CELLS
Description
Input cell with no pull up or down resistors
Input cell with 1KOhm pull up resistor
Input cell with 1KOhm pull down resistor
Input cell with 2KOhm pull up resistor
Input cell with 2KOhm pull down resistor
Input cell with 4KOhm pull up resistor
Input cell with 4KOhm pull down resistor
Input cell with 100KOhm pull up resistor
Input cell with 100K Ohm pull down resistor
Cell
NPIPNR
NPIPR1P
NPIPR1M
NPIPR2P
NPIPR2M
NPIPR3P
NPIPR3M
NPIPR4P
NPIPR4M
POWER SUPPLY CELLS
Cell
NPOPVP
NPOPVM
NPIBVP
NPIBVM
NPLAVP
NPLAVM
NPIBLAVP
Description
VDD power cell for Outputs
GND power cell for Outputs
VDD power cell for Buffers
GND power cell for Buffers
VDD power cell for Logic Array
GND power cell for Logic Array
VDD power cell for Buffer and Logic Array
Cell
NPLAVDD
NPLAGND
NPIBLAVDD
NPIBLAGND
NPALLVP
NPALLVM
NPALLVDD
Description
VDD power cell for Logic Array
GND power cell for Logic Array
VDD power cell for Buffer and Logic Array
GND power cell for Buffer and Logic Array
VDD power cell for All rails
GND power cell for All rails
VDD power cell for All rails
NPIBLAVM
GND power cell for Buffer and Logic Array
NPALLGND
GND power cell for All rails
Our Libraries are continually being enhanced, so please contact your local Design Centre for the latest information.
OSCILLATOR CELLS *
Description
1 to 5MHz Crystal Oscillator
5 to 20MHz Crystal Oscillator
15 to 40MHz Crystal Oscillator
Low Power 32KHz Crystal Oscillator
NPOSC1ENB
1 to 5MHz Crystal Oscillator with Pwr Down
NPOSC2ENB
5 to 20MHz Crystal Oscillator with Pwr Down
NPOSC3ENB
32KHz to 1MHz Crystal Osc. with Pwr Down
NPOSC4ENB
15 to 40MHz Crystal Osc. with Pwr Down
* In development, please confirm status with local Design Centre
Cell
NPOSC1
NPOSC2
NPOSC4
NPLPOSC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLR75000-QFP144P1.1SQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gate Array |
| CLR75000-QFP144P1.2SQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gate Array |
| CLR76000 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLR79 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Commercial Types TAT for CLR79 and TAX for CLR81 |
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