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參數(shù)資料
| 型號(hào)： | CLR75000 |
| 英文描述： | ASIC |
| 中文描述： | 專(zhuān)用集成電路 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 75K |
| 代理商： | CLR75000 |
ARRAY
RAW GATES
PADS
PACKAGE
CLR73000
12200
104
MQFP100
FQFP100
TQFP100
CLR74000
19100
128
MQFP120
MQFP128
CLR75000
30900
160
MQFP144
TQFP144
MQFP160
CLR76000
53900
208
FQFP208
CLR70000
1.0
μ
(0.8
μ
L eff) CMOS GATE ARRAYS
FEATURES
I
1.0
μ
(0.8
μ
Leff) twin well, epitaxial CMOS process
I
Architecture optimised for Quad Flat Packs
I
New peripheral design employing
state-of-the-art pad pitch
I
12K to 54K available gates on a channelless array
architecture
I
Low power consumption (<5
μ
W/gate/MHz)
I
Programmable slew controlled outputs.
I
24mA drive capability
I
ESD protection in excess of 2kV
I
Fully compatible with CLA70000’s extensive and
proven core libraries.
I
Supports JTAG/BIST test philosophies
(IEEE 1149-1 Test Procedures)
I
Design libraries available on Industry Standard
workstations
Description
Page
Process Technology
Core Design
2
2
I/O Design
Cell Libraries
2
3
DC Characteristics
Design Tools
4
5
Packaging
6
CLR70000 FAMILY
CONTENTS
GENERAL DESCRIPTION
Advances in process geometry have resulted in denser and
denser core logic. As a consequence the Industries ‘pad to
gate’ ratio (total number of pads vs number of available gates)
has been reducing and the number of pad limited designs is
rapidly increasing. The CLR70000 employs a completely new
design of peripheral cell which is based on a state-of-the-art
pad pitch allowing more pads per silicon area. The
architecture of the arrays has been optimised to suit the
popular JEDEC/EIAJ compliant QFP package types. Couple
this with the proven CLA70000 0.8
μ
(Leff) CMOS core and it’s
associated libraries and the CLR70000 is well positioned to
combat todays fast growing QFP and ‘pad limited’ CMOS
Gate Array applications.
DS3697-2.0
MARCH 1993
Photograph of Bonding Trials on CLR70000
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLR75000-QFP144P1.1SQ | Gate Array |
| CLR75000-QFP144P1.2SQ | Gate Array |
| CLR76000 | ASIC |
| CLT2020 | PHOTOTRANSISTOR | NPN | 200M | CAN-4.6 |
| CLT6053 | Optoelectronic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLR75000-QFP144P1.1SQ | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Gate Array |
| CLR75000-QFP144P1.2SQ | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Gate Array |
| CLR76000 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ASIC |
| CLR79 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Commercial Types TAT for CLR79 and TAX for CLR81 |
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