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參數資料
| 型號： | CLR75000 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數： | 3/7頁 |
| 文件大?。?/td> | 75K |
| 代理商： | CLR75000 |
CLR70000
2
CMOS PROCESS TECHNOLOGY
The CLR70000 arrays are based on GEC Plessey
Semiconductors well proven 0.8
μ
CMOS process,
manufactured at GPS’s advanced , Class 10, six-inch wafer
fabrication facility. The process is a twin well, self aligned
oxide-isolated technology, with an effective channel length of
0.8
μ
(1.0
μ
drawn ), giving a low defect density, high reliability,
and inherently low power dissipation. The process has
excellent immunity to latch-up, and ESD, and exhibits stable
performance characteristics.
Figure 1 : VQ’ Process Cross Section
CORE CELL DESIGN
The CLR70000 core is totally compatible with the well proven
CLA70000 core. A four transistor group (2 NMOS and 2
PMOS) (fig 2.) forms the basic cell of the core array. This array
element is repeated in a regular fashion over the complete
core area to give a homogeneous ‘Full Field’ (sea of gates)
array. This lends itself to hierarchical design, allowing pre-
routed user defined subcircuits to be repeated anywhere on
the array. The core cell structure has been carefully designed
to maximise the number of nets which may be routed through
the cell. This enables optimal routing for both data flow and
control signal distribution schemes thus giving very high
overall utilisation figures. This feature is of particular benefit
in designs using highly structured blocks such as memory or
arithmetic functions.
INPUT/OUTPUT BUFFER DESIGN
The CLR70000 employs a new generation of I/O cell taking
advantage of design and assembly advances and new
innovative pad layout techniques.
The peripheral cells are fully programmable as Input, Output,
VDD or GND, and they are designed to offer several
interfacing options, TTL and CMOS for example. The cells
already contain input ‘pull-up’ and ‘pull-down’ resistors and
Electro Static Discharge protection elements. Components
for implementing Schmitt Triggers, TTL threshold detectors,
tristate control, and flip-flops for signal re-timing are also
included. A range of output buffers is available with various
output drive currents to match system requirements.
Noise transients due to a large number of simultaneously
switching outputs are an increasing problem as bus widths
widen (The supply pad location, inductance of the bond wires
and package leads are also factors). CLR70000 Arrays offer
several I/O buffers with the capability to control the output slew
(di/dt) which are invaluable in controlling these transients
when driving large capacitive loads such as busses.
Figure 2 : Core Cell Design showing Cell Transparency
Figure 3 : CLR70000 Peripheral Cell
Programmable
contacts
VDD
Supply
VSS
Supply
Horizontal Routing
Channels on Metal 1
Vertical Routing Channels on Metal 2
Slew-controlled driver
D
INPUT
DATA
N N
P P
PIN
50pF
Driver
IB2BD
IBSK1
IBSK2
IBSK3
Delay(nsec)
2.57
3.81
4.90
6.72
Current Ramp (mA/nSec)
107.30
47.40
22.90
11.00
OPT3
2.5V
2.5V
Figure 4 : Slew Rate Control
Delay
INPUT
IB6
IB5
IB4
IB3
IB2
IB1
OUTPUT
Bonding
Pad
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| CLR75000-QFP144P1.1SQ | Gate Array |
| CLR75000-QFP144P1.2SQ | Gate Array |
| CLR76000 | ASIC |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CLR75000-QFP144P1.1SQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gate Array |
| CLR75000-QFP144P1.2SQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gate Array |
| CLR76000 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| CLR79 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Commercial Types TAT for CLR79 and TAX for CLR81 |
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