- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379899 > CLC935 (National Semiconductor Corporation) 12-bit, 15MSPS A/D Converter PDF資料下載
參數(shù)資料
| 型號： | CLC935 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-bit, 15MSPS A/D Converter |
| 中文描述： | 12位，15MSPS A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 271K |
| 代理商： | CLC935 |
9
http://www.national.com
Sine to ECL Conversion Circuit
For variable frequency CONVERT clocks, low-phase-
noise frequency synthesizers like the Fluke 6080A or the
HP8662 are good choices. Sinusoidal sources of this
type will require a sine-to-ECL conversion circuit, such
as the one above. This circuit operates consistently with
low level inputs (0dBm), but is sensitive to noise
(jitter) from the synthesizer. Maintaining a larger input
level (> +6dBm), greatly reduces this jitter contribution.
Output Coding
The CLC935 data converter is capable of producing four
possible digital output formats: offset binary, two’s com-
plement, and their inverted versions. In offset binary the
outputs count from 000h to FFFh, as the input varies from
-FS (full-scale) to +FS. For two’s complement output
coding, the MSB in the offset binary format is inverted.
D1
(MSB)
(pin 6) output rather than the D1(MSB) (pin 7).
When using inverted coding formats, the data outputs D2
- D12(LSB) are inverted by tying DATA INV (pin 25) to
an ECL logic HIGH (or grounding). For non-inverted
operation DATA INV should be left floating, or tied to an
ECL logic LOW.
On the CLC935 converter, this is achieved by using the
_____
Analog Input
Offset Binary
Two’s Complement
+FS - 1 LSB
+FS - 2 LSBs
+FS - 3 LSBs
-
-
mid-scale +
1/2
LSB
mid-scale -
1/2
LSB
-
-
-FS + 2 LSBs
-FS + 1 LSB
-FS
1111 1111 1111
1111 1111 1110
1111 1111 1101
-
-
1000 0000 0000
0111 1111 1111
-
-
0000 0000 0010
0000 0000 0001
0000 0000 0000
0111 1111 1111
0111 1111 1110
0111 1111 1101
-
-
0000 0000 0000
1111 1111 1111
-
-
1000 0000 0010
1000 0000 0001
1000 0000 0000
Output Data and “Data Ready”
The CLC935 has data latency of one clock cycle. This
means that a sample taken on the rising edge of
CONVERT (t
N
) will appear at the output on the t
N+1
clock
cycle of the CLC935. The internally latched data from
the previous conversion (t
N-1
CLC935) is latched to
the digital outputs on the rising edge of CONVERT. The
previous output data is guaranteed to be valid for at least
tHLD after the rising edge of CONVERT and the new
output data will be stable t
DV
after the rising edge of
CONVERT (see timing diagram).
Since the output data is synchronous with the rising edge
of the CONVERT, its falling edge should be used to
generate the output latch clock, or DATA READY signal, if
the system so requires. This will limit the bulk of the digital
switching noise to a period well away from the sensitive
analog processing inside the data converter. The use of
the rising edge of CONVERT for Data Ready, and buffer
clocking signals, is not recommended. Separate drivers
for CONVERT and output latch strobing should be used to
minimize corruption and jitter in the CONVERT signal.
Digital Interface and Termination Differences
All high-resolution A/D converters are susceptible to
performance degradation if interference from the digital
outputs is allowed to couple back to the analog input.
Capacitive coupling back to the A/D input can result in
increased harmonic distortion, or an elevated noise floor.
This “noise” tends to be highly correlated to the input
signal, and is difficult to remove through standard DSP
noise reduction techniques. To minimize this effect, the
CLC935 data converter employs ECL “compatible”
outputs rather than larger swing TTL compatible outputs.
Additional measures to reduce output-to-input coupling
have resulted in some slight differences when interfacing
to the data converter outputs as compared with true ECL.
Significant system power and digital noise reduction for
the CLC935 data converter results from the use of on
chip ECL pull-down sources for each of the twelve bit
lines as illustrated in the figure below. As shown, series
termination resistors are included on each data bit in
order to drive external 50
transmission lines (i.e. PCB
traces with Zo = 50
).
Internal ECL Termination Circuit
The CLC935 data converter outputs are 10KH ECL logic
compatible with internal constant-current pull-downs, and
are designed to be connected directly to 10KH level
inputs with no external termination. The power dissipa-
tion in each termination is the 6mA standing current,
multiplied by the 5.2V supply, or 31mW per output. For a
12-bit data converter, this represents 375mW. When
compared to external (50
/-2V) Thevenin terminations,
the power savings is 1.2W.
Output Latching and Level Translation
Parasitic capacitances and inductances should be minimized,
when interfacing to the CLC935 outputs. Output latches
(10176) or buffers should be placed as close as practical to
the output pins. If these output latches drive a significant
trace load on the same board as the data converter, differen-
tial output latches (100151) and trace routing should be used.
V
BB
130
CLC935
CONV
CONV
-5.2V
10114
SINE
WAVE
0.5V
pp
130
50
50
50
0.1
μ
F
0.1
μ
F
81
81
-5.2V
47
6mA
Digital Outputs
D1 thru D12
CLC935
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC935B8C | 12-bit, 15MSPS A/D Converter |
| CLC935BC | 12-bit, 15MSPS A/D Converter |
| CLC949 | Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter |
| CLC949ACQ | Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter |
| CLC949AJQ | Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC935A8C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| CLC935A8CX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| CLC935AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| CLC935B8C | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-bit, 15MSPS A/D Converter |
| CLC935BC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-bit, 15MSPS A/D Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。