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參數(shù)資料
| 型號： | CLC935 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-bit, 15MSPS A/D Converter |
| 中文描述： | 12位，15MSPS A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 271K |
| 代理商： | CLC935 |
5
http://www.national.com
Discussion of CLC935 Plots and Specifications
Some of the preceding performance plots require
more explanation than is feasible in the caption. This
section goes into more detail as to how these plots
were generated, and how they might be utilized. Additional
information can be found in the application note AD-01 ...
“Designing with High-Performance A/D converters”.
Spectral Plots
Three frequency spectrum plots are shown for the
CLC935 ADC. Low and High “Nyquist - band” (<Fs/2) sin-
gle tone input frequencies were selected along with a
“super - Nyquist” (>Fs/2) tone. FFT analysis were per-
formed using 4K point (4096), rectangular windowed
data. Valid ADC input frequencies were chosen to land
within the center of a prime numbered FFT frequency bin.
SFDR and SNR vs. Input level Plots
Fixed frequency input amplitude sweeps were run and
the 4K point FFT analysis summary plotted for the three
Spectral Plot input frequencies. Signal to Noise Ratio
(SNR) is the power ratio between the fundamental and
the spectral noise (the first 10 harmonics are excluded
from the noise power calculation). As the signal level is
reduced from full scale, the noise power remains
relatively constant. This results in a backward declining
straight line shown as SNR vs Input Amplitude. In some
converters the ‘noise’ is not independent of the input
signal level and hence the line’s slope may vary.
The Spur-Free Dynamic Range (SFDR) performance is
less uniform. SFDR is the magnitude ratio of the funda-
mental to the next largest spectral line. ADC differential &
integral linearity, along with sample to sample step
magnitude, create a unique spectral response for each
ADC and operating condition. Because sub-ranging
ADCs are susceptible to conversion errors at their
“coarse-quantization” thresholds (see Principle of
Operation), spectral variations become less predictable
at these operating points. Special care has been taken in
the design of these converters to minimize the character-
istic SFDR performance dip in the -20 to -40 dBFS input
amplitude ranges.
SNR and SFDR vs. Conversion Rate
The CLC935 converter has an asynchronous timing
schemes which are triggered by the rising edge of the
CONVERT clock. When the conversion cycle is com-
plete, the T/H amplifier resumes its “track” mode of oper-
ation. Because of this timing scheme, ADC performance
is relatively independent of sample rate.
SNR, and SFDR vs. Input Frequency
These plots show the variation in converter performance
relative to analog input frequency. Input frequencies to
about 65MHz (the Large Signal Bandwidth) are included,
and can be useful for under-sampled applications.
Beyond the Large Signal Bandwidth, performance for
large signals degrades quickly. The small-signal-band-
width (measured with analog inputs below 500mV
pp
)
performance does not degrade until around 135MHz.
Two Tone Linearity Spectrum
In a linear system, the input signal can be viewed math-
ematically as a superposition of sinusoids (Fourier
Transform). The system output can be predicted by the
superpositioning of the individual effects on each of
the sinusoid inputs. For example, if a linear network is
presented with a single tone signal F
1
and the result is an
attenuation by a factor A
1
, and it is then presented with
another frequency F
2
attenuated by A
2
through the
system, then the expected output for an input of F
1
+F
2
would be A
1
F
1
+ A
2
F
2
. If the network is not linear, the
output will contain frequency components in addition to
those present at the input. The most common products
likely to be present in the output are at MF
1
±NF
2
, where
M and N are integers, and F1 and F2 are the two input
frequencies.
In the
Two-Tone IMD
plots, two sinusoids are passively
filtered and summed to comprise the ADC input. The
V
in
peak-to-peak magnitude is set so that the ADC is
operating at -1dBFS and the test tone frequencies are
shown on the various plots.
Differential & Integral Linearity plots
Differential Non-Linearity (DNL) is computed by collect-
ing a large data series and calculating the difference
between its code density and the code density of an ideal
sine-wave. The ADC is sampled at its rated maximum
conversion rate with a low frequency (approx 400kHz), -
1dBFS sine-wave input. The Integral Non-Linearity (INL)
is computed by fitting the summed DNL data to a straight
line. Deviations of either DNL or INL are usually specified
in fractional Quantization levels (LSBs). DNL describes
the code to code uniformity.
Digital I/O Timing plot
The digital outputs make their transition and become
valid TDVns after the rising edge of the CONVERT
signal. The actual time to this transition varies slightly
from output bit to output bit. The amount of this variation
is small and well within the timing needs of most
systems. In the I/O Timing plot, the transition of the 6
most significant output bits are shown with reference to
the CONVERT clock.
Noise Power Ratio (NPR) plots
NPR testing simulates multichannel communication
applications. The ADC input is comprised of broadband
random noise (Nyquist band limited) with a deep, narrow
band of noise notched out. The NPR is simply the depth
of the notch in the FFT spectrum. The non-coherent
nature of the input signal requires that the data be win-
dowed in order to minimize spectral “l(fā)eakage” into adja-
cent FFT filter bins. A four term window function similar to
Blackman-Harris was used on 4K point data sets and 10
FFT results were averaged. The input power is varied
until a peak NPR figure is found. Distortion products from
outside the notched band fall into the FFT notch and
degrade NPR. Thus, channel to channel isolation can be
determined.
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PDF描述 |
|---|---|
| CLC935B8C | 12-bit, 15MSPS A/D Converter |
| CLC935BC | 12-bit, 15MSPS A/D Converter |
| CLC949 | Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter |
| CLC949ACQ | Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter |
| CLC949AJQ | Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC935A8C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| CLC935A8CX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| CLC935AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| CLC935B8C | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-bit, 15MSPS A/D Converter |
| CLC935BC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-bit, 15MSPS A/D Converter |
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