參數(shù)資料
型號: CLC5903
廠商: National Semiconductor Corporation
英文描述: Dual Digital Tuner / AGC
中文描述: 雙數(shù)字調(diào)諧器/自動增益控制
文件頁數(shù): 8/29頁
文件大?。?/td> 698K
代理商: CLC5903
www.national.com
8
C
D[7:0]
62,63,
69:73,75
J9,L10,
M12,K11,
L12,H9,
J11,H10
DATA BUS.
Active high
This is the 8 bit control data I/O bus. Control register data is loaded into the chip or
read from the chip through these pins. The chip will only drive output data on these
pins when
CE
is low,
RD
is low, and
WR
is high.
A[7:0]
48,50,
52:57
M5,L6,L7,
K7,L8,M8,
K8,L9
ADDRESS BUS.
Active high
These pins are used to address the control registers within the chip. Each of the con-
trol registers within the chip are assigned a unique address in a flat address space. A
control register can be written to or read from by setting
A[7:0]
to the register’s
address.
RD
59
K9
READ ENABLE.
Active low
This pin enables the chip to output the contents of the selected register on the
D[7:0]
pins when
CE
is also low.
WR
58
M9
WRITE ENABLE.
Active low
This pin enables the chip to write the value on the
D[7:0]
pins into the selected regis-
ter when
CE
is also low. This pin can also function as
RD/WR
if
RD
is held low.
CE
60
J8
CHIP ENABLE.
Active low
This control strobe enables the read or write operation. The contents of the register
selected by
A[7:0]
will be output on
D[7:0]
when
RD
is low and
CE
is low. If
WR
is low
and
CE
is low, then the selected register will be loaded with the contents of
D[7:0]
.
TDO
116
B6
TEST DATA OUT.
Active high
TDI
117
C6
TEST DATA IN.
Active high with pull-up
TMS
118
B5
TEST MODE SELECT.
Active high with pull-up
TCK
119
A5
TEST CLOCK.
Active high
. Tie low if JTAG is not used.
TRST
121
B4
TEST RESET.
Active low with pull-up
Asynchronous reset for TAP controller. Tie low or to
MR
if JTAG is not used.
SCAN_EN
122
A4
SCAN ENABLE.
Active low with pull-up
Enables access to internal scan registers. Tie high. Used for manufacturing test only!
VSS
19,51,76,
103,120
C5,D8,F1,
J12,L2,M7
Core Ground. Quantity 5 in PQFP (6 in FBGA).
VDD
21,49,74,
85,115
A6,F11,G1,
K12,M6
Core Power, 1.8V. Quantity 5.
VSSIO
3,29,47,61,
68,83,89,
98,110
A8,B2,C10,
E10,G11,
J10,K6,M10
I/O Ground. Quantity 9 (8 in FBGA).
VDDIO
11,39,64,
79,92,107,
128
A2,A9,D10,
H12,M2,
M11
I/O Power, 3.3V. Quantity 7 (6 in FBGA).
NC
1,2,37,44,
65,66,67,
100,101,
102,123
A11,A12,
B3,B10,C3,
C9,J7,K10,
L11,L5,L3,
M1
No Connect. These pins should be left floating. Quantity 11 (12 in FBGA).
Pin Descriptions
(Continued)
Signal
PQFP Pin
FBGA Pin
Description
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