參數(shù)資料
型號(hào)： CLC5903
廠商： National Semiconductor Corporation
英文描述： Dual Digital Tuner / AGC
中文描述： 雙數(shù)字調(diào)諧器/自動(dòng)增益控制
文件頁(yè)數(shù)： 22/29頁(yè)
文件大小： 698K
代理商： CLC5903
www.national.com
22
C
AGC_IC_B
1B
R/W
0
24
7:0
AGC fixed gain for channel B. Format is an 8-bit, unsigned magnitude number. The channel
B DVGA gain will be set to the inverted three MSBs.
AGC_RB_A
1B
R
0
25
7:0
AGC integrator readback value for channel A. Format is an 8-bit, unsigned magnitude num-
ber. The user can read the magnitude MSBs of the channel A integrator from this register.
AGC_RB_B
1B
R
0
26
7:0
AGC integrator readback value for channel B. Format is an 8-bit, unsigned magnitude num-
ber. The user can read the magnitude MSBs of the channel B integrator from this register.
TEST_REG
14b
R/W
0
27(LSBs)
28(MSBs)
7:0
5:0
Test input source. Instead of processing values from the
A
|
BIN
pins, the value from this
location is used instead. Format is 14-bit 2s complement number spread across 2 regis-
ters.
Reserved
1B
-
-
29
7:0
For future use.
Reserved
1B
-
-
30
7:0
For future use.
DEBUG_EN
1b
R/W
0
31
0
0=Normal. 1=Enables access to the internal probe points.
DEBUG_TAP
5b
R/W
0
31
5:1
Selects internal node tap for debug.
0 selects F1 output for BI, 20 bits
1 selects F1 output for BQ, 20 bits
2 selects F1 output for AQ, 20 bits
3 selects F1 output for AI, 20 bits
4 selects F1 input for BI, 20 bits
5 selects F1 input for BQ, 20 bits
6 selects F1 input for AI, 20 bits
7 selects F1 input for AQ, 20 bits
8 selects NCO A, cosine output. 17 bits, 3 LSBs are 0.
9 selects NCO A, sine output, 17 bits, 3 LSBs are 0.
10 selects NCO B, cosine output, 17 bits, 3 LSBs are 0.
11 selects NCO B, sine output, 17 bits, 3 LSBs are 0.
12 selects NCO AI, rounded output, 15 bits, 5 LSBs are 0.
13 selects NCO AQ, rounded output, 15 bits, 5 LSBs are 0.
14 selects NCO BI, rounded output, 15 bits, 5 LSBs are 0.
15 selects NCO BQ, rounded output, 15 bits, 5 LSBs are 0.
16-31 selects AGC CIC filter output. 9 MSBs from ch A, next 9 bits from ch B, 2 LSBs are 0.
DITH_A
1b
R/W
1
31
6
0=Disable NCO dither source for channel A. 1=Enable.
DITH_B
1b
R/W
1
31
7
0=Disable NCO dither source for channel B. 1=Enable.
AGC_TABLE
32B
R/W
0
128-159
7:0
RAM space that defines key AGC loop parameters. Format is 32 separate 8-bit, 2’s com-
plement numbers. This is common to both channels.
F1_COEFF
22B
R/W
0
160-181
7:0
Coefficients for F1. Format is 11 separate 16-bit, 2’s complement numbers, each one
spread across 2 registers. The LSBs are in the lower registers. For example, coefficient
h0[7:0] is in address 160, h0[15:8] is in address 161, h1[7:0] is in address 162, h1[15:8] is
in address 163. PAGE_SEL_F1=1 maps these addresses to coefficient memory B.
F2_COEFF
64B
R/W
0
182-245
7:0
Coefficients for F2. Format is 32 separate 16-bit, 2’s complement numbers, each one
spread across 2 registers. The LSBs are in the lower registers. For example, coefficient
h0[7:0] is in address 182, h0[15:8] is in address 183, h1[7:0] is in address 184, h1[15:8] is
in address 185. PAGE_SEL_F2=1 maps these addresses to coefficient memory B.
COEF_SEL_F1A
1b
R/W
0
246
0
Channel A F1 coefficient select register. 0=memory A, 1=memory B.
COEF_SEL_F1B
1b
R/W
0
246
1
Channel B F1 coefficient select register. 0=memory A, 1=memory B.
PAGE_SEL_F1
1b
R/W
0
246
2
F1 coefficient page select register. 0=memory A, 1=memory B.
COEF_SEL_F2A
1b
R/W
0
247
0
Channel A F2 coefficient select register. 0=memory A, 1=memory B.
COEF_SEL_F2B
1b
R/W
0
247
1
Channel B F2 coefficient select register. 0=memory A, 1=memory B.
PAGE_SEL_F2
1b
R/W
0
247
2
F2 coefficient page select register. 0=memory A, 1=memory B.
SFS_MODE
1b
R/W
0
248
0
0=
SFS
asserted at the start of each output word when PACKED=1 or each I/Q pair when
PACKED=0, 1=
SFS
asserted at the start of each output sample period.
SDC_EN
1b
R/W
0
248
1
0=normal serial mode, 1=serial daisy-chain master mode.
AGC_COMB_ORD
2b
R/W
0
249
1:0
Enable reduced bandwidth AGC power detector. 0=2
nd
-order decimate-by-eight CIC,
1=1-tap comb added to CIC, 2=4-tap comb added to CIC.
EXT_DELAY
5b
R/W
0
249
6:2
Number of
CK
period delays in excess of 4 needed to align the DVGA gain step with the
digital gain compensation step. Use the default of zero for the CLC5957 ADC.
a. These are the default values set by a master reset (
MR
). Sync in (
SI
) will not affect any of these values.
Condensed CLC5903 Address Map
Register Name
Addr
Addr
Hex
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DEC
0
0x00
Dec7
Dec6
Dec5
Dec4
Dec3
Dec2
Dec1
Dec0
Control Register Addresses and Defaults
(Continued)
Register Name
Width
Type
Default
a
Addr
Bit
Description
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