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參數(shù)資料
| 型號(hào)： | CLC5523IN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Low-Power, Variable Gain Amplifier |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP8 |
| 封裝： | PLASTIC, MDIP-8 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大小： | 154K |
| 代理商： | CLC5523IN |
http://www.national.com
10
Digital Gain Control
Digitally variable gain control can be easily realized
by driving the CLC5523’s gain control input with a
digital-to-analog converter (DAC). Figure 10 illustrates
such an application. This circuit employs National
Semiconductor’s eight-bit DAC0830, the LM351 JFET
input op-amp, and the CLC5523 VGA. With V
ref
set to 2V,
the circuit provides up to 80dB of gain control in
512 steps with up to 0.05% full scale resolution. The
maximum gain of this circuit is 20dB.
Figure 10: Digital Gain Contro
l
Automatic Gain Control (AGC) #1
Fast Response AGC Loop
The AGC circuit shown in Figure 11 will correct a 6dB
input amplitude step in 100ns. The circuit includes a two
op-amp precision rectifier amplitude detector (U1 and
U2), and an integrator (U3) to provide high loop gain at
low frequencies.The output amplitude is set by R9.
Some notes on building fast AGC loops:
Precision rectifiers work best with large output signals.
Accuracy is improved by blocking DC offsets, as shown in
Figure 11.
Signal frequencies must not reach the gain control port of
the CLC5523, or the output signal will be distorted
(modulated by itself).
A fast settling AGC needs
additional filtering beyond the integrator stage to
block signal frequencies. This is provided in Figure 11
by a simple R-C filter (R10 and C3); better distortion
performance can be achieved with a more complex filter.
These filters should be scaled with the input signal
frequency.
Loops with slower response time (longer
integration time constants) may not need the R10 –
C3 filter.
Checking the loop stability can be done by monitoring the
V
g
voltage while applying a step change in input signal
amplitude. Changing the input signal amplitude can be
easily done with either an arbitrary waveform generator
or a fast multiplexer such as the CLC532.
Automatic Gain Control (AGC) #2
Figure 12 on the following page, illustrates an automatic
gain control circuit that employs two CLC5523’s. In this
circuit, U1 receives the input signal and produces an
output signal of constant amplitude. U2 is configured
to provide negative feedback. U2 generates a rectified
gain control signal that works against an adjustable
bias level which may be set by the potentiometer and
R
b
. C
i
integrates the bias and negative feedback. The
resultant gain control signal is applied to the U1 gain
control input V
g
.
The bias adjustment allows the U1
output to be set at an arbitrary level less than the
maximum output specification of the amplifier.
Rectification is accomplished in U2 by driving both
the amplifier input and the gain control input with the
U1 output signal. The voltage divider that is formed
by R1, R2 and the V
g
input (pin 1) resistance, sets the
rectifier gain.
CLC5523 Applications
CLC5523
R
f
1k
2
3
4
1
6
7
25
W
R
G
100
W
V
o
V
in
-
LM351
+
DAC0830
I
o2
I
o1
R
fb
V
ref
Digital
Input
+
-
CLC5523
R
f
Output
20MHz,
0.1V
pp
V
in
R
g
100
W
2
3
4
1
6
7
-
+
U3
CLC426
R10
500
W
C3
40pF
C2
680pF
R9
4.22k
-5V
R8
500
W
R7
500
W
+
-
U2
CLC404
R5
25
W
R6
500
W
-
+
U1
CLC404
1N5712
Schottky
R3
500
W
R4
500
W
R2
25
W
R1
20
W
C1
1.0
m
F
Includes scope
probe capacitance
Figure 11: Automatic Gain Control Circuit #1
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| CLC5526MSAX/NOPB | 功能描述:IC AMP DIG VARIABLE GAIN 20-SSOP RoHS:是 類(lèi)別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 放大器類(lèi)型:電壓反饋 電路數(shù):4 輸出類(lèi)型:滿擺幅 轉(zhuǎn)換速率:33 V/µs 增益帶寬積:20MHz -3db帶寬:30MHz 電流 - 輸入偏壓:2nA 電壓 - 輸入偏移:3000µV 電流 - 電源:2.5mA 電流 - 輸出 / 通道:30mA 電壓 - 電源，單路/雙路(±):4.5 V ~ 16.5 V，±2.25 V ~ 8.25 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
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