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參數(shù)資料
| 型號： | CLC031A |
| 廠商： | Motorola, Inc. |
| 英文描述： | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs |
| 中文描述： | 的SMPTE 292M/259M數(shù)字視頻解串器/解擾器的視頻和輔助數(shù)據(jù)FIFO |
| 文件頁數(shù)： | 29/31頁 |
| 文件大?。?/td> | 399K |
| 代理商： | CLC031A |
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Application Information
(Continued)
output timing practices, especially critical at HD data rates.
The power pins feeding the I/O should have low inductance
connections to the power and ground planes. It is recom-
mended that these connections use at least two vias per
power or ground pin. Short interconnecting traces consistent
with good layout practices and soldering rules must be used.
Sampling or clocking of data by external devices should be
so timed as to take maximum advantage of the steady-state
portion of the parallel output data interval. The CLC031A is
designed so that video data will be stable at the positive-
going transition of V
. Data should not be sampled close
to the data transition intervals associated with the negative-
going clock edge. The specified propagation delay and clock
to data timing parameters must be observed. When data is
being sampled from the video data port together with the
ANC port and/or I/O port, it is recommended that the sam-
pling clocks be synchronized with the video clock, V
, to
minimize possible effects from ground bounce or output
droop on sampled signal levels.
PROCESSING NON-SUPPORTED RASTER FORMATS
The number and type of HD raster formats has proliferated
since the CLC031A was designed. Though not specifically
capable of fully or automatically processing these new for-
mats, the CLC031A may still be capable of deserializing
them. The user is encouraged to experiment with processing
these formats, keeping in mind that the CLC031A has not
been tested to handle formats other than those detailed in
Table 4
. Therefore, the results from attempts to process
non-supported formats is not guaranteed. The following
guidelines concerning device setup are provided to aid the
user in configuring the CLC031A to attempt limited process-
ing of these other raster formats.
In general, the device is configured to defeat its automatic
format detection function and to limit operation to a general
HD format. (The user should consult
Table 4
for guidance on
the format groups similar to the non-supported one to be
processed). Since most non-supported formats are in the
HD group, the CLC031A should be configured to operate in
HD-ONLY mode by setting bit-5 of the FORMAT 0 register
(address 0Bh). Also, the device should be further configured
by loading the FORMAT SET[4:0] bits of this register with the
general HD sub-format code. The complete data word for
this general HD sub-format code with HD-ONLY bit set is
33Fh. Since this format differs from those in the table, the
EAV/SAV indicators are disabled. Without these indicators,
line numbering and CRC processing are disabled and ANC
data extraction will not function. Output video chroma and
luma data will be word-aligned. Post-processing of the par-
allel data output from the CLC031A will be needed to imple-
ment CRC checking or line number tracking.
USING EXTERNAL VCXO FOR VCLK
The
EXTERNAL V
bit of
VIDEO CONTROL 0
(register
address 55h) is a special application function which enables
use of an external VCXO as a substitute for the internally
generated V
. Additional circuitry is enabled within the
CLC031A which provides phase-frequency detection and
control voltage output for the VCXO. An external loop filter
and voltage amplifier are required to interface the control
voltage output to the VCXO frequency control input. When
this function is used, the
R
BB
output function is changed
from the bias supply output to the control voltage output of
the phase-frequency detector. The V
output changes
function, becoming the input for the VCXO signal.
Figure 7
shows an example using dual VCXOs for V
CLK
to
handle both standard and high definition video.
C
www.national.com
29
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