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參數(shù)資料
| 型號： | CLC031 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs |
| 中文描述： | 的SMPTE 292M/259M數(shù)字視頻解串器/解擾器的視頻和輔助數(shù)據(jù)FIFO |
| 文件頁數(shù)： | 25/31頁 |
| 文件大?。?/td> | 383K |
| 代理商： | CLC031 |
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Device Operation
(Continued)
VIDEO CONTROL 0 (register address 55h)
The
EXTERNAL V
CLK
bit is a special application function
which enables use of an external VCXO as a substitute for
the internally generated V
. Additional circuitry is enabled
within the CLC031 which provides phase-frequency detec-
tion and control voltage output for the VCXO. An external
loop filter and voltage amplifier are required to interface the
control voltage output to the VCXO frequency control input.
When this function is used, the
R
BB
output function is
changed from the bias supply output to the control voltage
output of the phase-frequency detector. The V
CLK
output
changes function, becoming the input for the VCXO signal.
Use of this function and required external support circuitry is
explained in the
Application Information
section.
The
SYNC DETECT ENABLE
bit, when set, enables detec-
tion of TRS characters. This bit is normally set (ON).
The
LSB CLIP ENABLE
bit, when set, causes the two LSBs
of TRS characters to be set to 00b as described in ITU-R
BT.601. This function is normally set (ON).
The
NRZI ENABLE
bit, when set, enables data to be con-
verted from NRZI to NRZ. This bit is normally set (ON).
The
DE-SCRAMBLE ENABLE
bit, when set, enables de-
scrambling of the incoming data according to requirements
of SMPTE 259M or SMPTE 292M. This bit is normally set
(ON).
CAUTION:
The default state of this register is 36h. If any of
the normal operating features of the descrambler are turned
off, this register’s default data must be restored to resume
normal device operation.
REFERENCE CLOCK REGISTER (Address 67h)
The
Reference Clock
register controls operation of the CDR
reference clock source. The
CLKEN
bit when reset to a
logic-0 enables the oscillator signal to be used by the
CLC031 as a reference. The default state of this bit at
power-on is enabled. In general, this function and bit should
not be disabled. The
INT_OSC EN
bit enables the internal
crystal oscillator amplifier. By default this bit is a logic-0 and
is therefore inactive at power-on. The device expects an
external 27MHz reference reference clock source to be con-
nected to the
XTALi/Ext Clk
pin and activated at power-on.
I/O PIN 0 THROUGH 7 CONFIGURATION REGISTERS
(Addresses 0Fh through 16h)
The
I/O Pin Configuration Registers
are used to map
individual bits of the multi-function I/O port to selected bits of
the Configuration and Control Registers.
Table 6
gives the
pin select codes for the Configuration and Control register
functions that may be mapped to the port.
Pin[n] Select [5]
controls whether the port pin is input or output. The port pin
will be an input when this bit is set and an output when reset.
Input-only functions may not be configured as outputs and
vice versa. The remaining five
Pin[n] Select [4:0]
bits iden-
tify the particular Control Register bit to be mapped.
Example:
Program, via the AD port, I/O port bit 0 as output
for the CRC Luma Error bit in the control registers.
1.
Set
ANC/CTRL
to a logic-low.
2.
Set
RD/WR
to a logic-low.
3.
Present 00Fh to
AD[9:0]
as the
I/O PIN 0 CONFIG
register address.
4.
Toggle
A
CLK
.
5.
Present 310h to
AD[9:0]
as the register data, the bit
address of the CRC Luma Error bit in the control regis-
ters.
6.
Toggle
A
CLK
.
C
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