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參數(shù)資料
| 型號： | CLC031 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs |
| 中文描述： | 的SMPTE 292M/259M數(shù)字視頻解串器/解擾器的視頻和輔助數(shù)據(jù)FIFO |
| 文件頁數(shù)： | 16/31頁 |
| 文件大?。?/td> | 383K |
| 代理商： | CLC031 |
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Device Operation
(Continued)
TEST PATTERN GENERATOR (TPG) AND BUILT-IN
SELF-TEST (BIST)
The CLC031 includes an on-board, parallel video
test pat-
tern generator (TPG)
. Four test pattern types are available
in both HD and SD formats, NTSC and PAL standards, and
4x3 and 16x9 raster sizes. The test patterns are: flat-field
black, PLL pathological, equalizer (EQ) pathological and a
75%, 8-colour vertical bar pattern. The pathologicals follow
recommendations contained in SMPTE RP 178-1996 re-
garding the test data used. The colour bar pattern has op-
tional bandwidth limiting coding in the chroma and luma data
transitions between bars. The
VPG FILTER ENABLE
bit in
the
VIDEO INFO 0
control register enables the colour bar
filter function. The test pattern data is available at the video
data outputs,
DV[19:0]
with a corresponding parallel rate
clock,
VCLK
, appropriate to the particular standard and
format selected.
The
TPG
also functions as a
built-in self-test (BIST)
which
can be used to verify device functionality. The
BIST
function
performs a comprehensive go/no-go test of the device. The
test may be run using any of the HD colour bar patterns or
one of two SD patterns, either the 270 Mb/s NTSC colour bar
or the PAL PLL pathological, as the test data pattern. Data is
input from the digital processing block, processed through
the device and tested for errors using either the EDH system
for SD or the CRC system for HD. Clock signals from the
CDR block supply timing for the test data. The CDR must be
supplied a 27MHz reference clock via the
XTALi/Ext Clk
input (or using the internal oscillator and crystal) during the
TPG
or
BIST
function. A go/no-go indication is logged in the
Pass/Fail
bit of the
TEST 0
control register set. This bit may
be assigned as an output on the multifunction I/O port.
TPG
and
BIST
operation is initiated by loading the code for
the desired test pattern into the
Test Pattern Select[5:0]
bits
and by setting the
TPG Enable
bit of the
TEST 0
register.
Note that when attempting to use the TPG or BIST immedi-
ately after the device has been reset or powered on, the TPG
defaults to the 270Mbps SD rate. The device must be con-
figured for the desired test pattern by loading the appropriate
code in to the
TEST 0
register. If HD operation is desired,
selection of the desired HD test pattern is sufficient to enable
the device to configure itself to run at the correct rate and
generate valid data.
Table 5
gives the available test patterns
and codes.
The
Pass/Fail
bit in the control register gives the device test
status indication. If no errors have been detected, this bit will
be set to logic-1 approximately 2 field intervals after
TPG
Enable
is set. If errors have been detected in the internal
circuitry of the CLC031,
Pass/Fail
will remain reset to a
logic-0. TPG or BIST operation is stopped by resetting the
TPG Enable
bit. Parallel output data is present at the
DV[19:0]
outputs during TPG or BIST operation.
Example:
Enable the TPG Mode to use the NTSC 270Mbps
colour bars as the BIST and TPG pattern. Enable TPG
operation using the I/O port.
1.
Set
ANC/CTRL
to a logic-low.
2.
Set
RD/WR
to a logic-low.
3.
Present 00Dh to
AD[9:0]
as the
TEST 0
register ad-
dress.
4.
Toggle
A
CLK
.
5.
Present 343h to
AD[9:0]
as the register data (525 line,
30 frame, 27MHz, NTSC 4x3, colour bars (SMPTE
125M)).
6.
Toggle
A
CLK
.
7.
The
PASS/FAIL
indicator,
TEST 0
register, Bit 7, should
be read for the result of the test. Alternatively, this bit
may be mapped to a convenient bit of the Multi-function
I/O bus. The test pattern data and clock is available at
the
DV[19:0]
and
V
CLK
outputs.
CONFIGURATION AND CONTROL REGISTERS
The configuration and control registers store data which
determines the operational modes of the CLC031 or which
result from its operation. Many of these registers may be
assigned as external I/O functions which are then available
on the multi-function I/O bus. These functions are summa-
rized in
Table 1
and detailed in
Table 2
. The power-on default
condition for the multi-function I/O port is indicated in
Table 1
and detailed in
Table 6
.
C
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