參數(shù)資料
型號(hào)： CLC014
廠商： National Semiconductor Corporation
英文描述： Adaptive Cable Equalizer for High-Speed Data Recovery(應(yīng)用于高速數(shù)據(jù)恢復(fù)的可調(diào)電纜均衡器)
中文描述： 高自適應(yīng)電纜均衡器高速數(shù)據(jù)恢復(fù)（應(yīng)用于高速數(shù)據(jù)恢復(fù)的可調(diào)電纜均衡器）
文件頁(yè)數(shù)： 8/18頁(yè)
文件大小： 519K
代理商： CLC014
Pin Definitions
Name
Pin
#
8, 9
13,
14
6, 7
Description
DI, DI
DO, DO
Differential data inputs.
Differential collector data
outputs (ECL compatible).
AEC loop filter pins.
A capacitor connected
between these pins governs
the loop response for the
adaptive equalization loop.
Eye monitor output. The
output of the equalization
filter.
Carrier detect. (Low when no
signal is present).
Output MUTE. (Active low.)
Carrier detect may be tied to
this pin to inhibit the output
when no signal is present.
Positive supply pins (ground
or +5V).
Negative supply pins (5.2V
or ground).
AEC+,
AEC
OEM
3
CD
5
MUTE
12
V
CC
1, 2,
4
10,
11
V
EE
Operation
The CLC014 Adaptive Cable Equalizer provides a complete
solution for equalizing high-bit-rate digital data transmitted
over long transmission lines. The following sections furnish
design and application information to assist in completing a
successful design:
Block diagram explanation of the CLC014
Recommended standard input and output interface con-
nections
Common applications for the CLC014
Measurement, PC layout, and cable emulation boxes
For applications assistance in the U.S., call 800-272-9959 to
contact a technical staff member.
BLOCK DESCRIPTION
The CLC014 is an adaptive equalizer that reconstructs serial
digital data received from transmission lines such as coaxial
cable or twisted pair. Its transfer function approximates the
reciprocal of the cable loss characteristic. The block diagram
in Figure 2 depicts the main signal conditioning blocks for
equalizing digital data at the receiving end of a cable. The
CLC014 receives baseband differential or single-ended digi-
tal signals at its inputs DI and DI.
The
Equalizer
block is a two-stage adaptive filter. This filter
is capable of equalizing cable lengths from zero meters to
lengths that require 40 dB of boost at 200 MHz.
The
Quantized Feedback Comparator
block receives the
differential signals from the equalizer filter block. This block
includes two comparators. The first comparator incorporates
a self-biasing DC restore circuit. This is followed by a second
high-speed comparator with output mute capability. The sec-
ond comparator receives and slices the DC-restored data.
Its outputs DO and DO are taken from the collectors of the
output transistors. MUTE latches DO and DO when a TTL
logic low level is applied.
The
Adaptive Servo Control
block produces the signal for
controlling the filter block, and outputs a voltage proportional
to cable length. It receives differential signals from the output
of the filter block and from the quantized-feedback compara-
tor (QFBC) to develop the control signal. The servo loop re-
sponse is controlled by an external capacitor placed across
the AEC+ and AEC pins. Its output voltage, as measured
differentially across AEC+ and AEC, is roughly proportional
to the length of the transmission line. For Belden 8281 co-
axial cable this differential voltage is about 1.5 mV/meter.
Once this voltage exceeds 500 mV, no additional equaliza-
tion is provided.
The
Carrier Detect (CD)
block monitors the signal power out
of the equalizing filter and compares it to an internal refer-
ence to determine if a valid signal is present. A CMOS high
output indicates that data is present. The output of CD can
be connected to the MUTE input to automatically latch the
outputs (DO and DO), preventing random transitions when
no data is present.
The
Output Eye Monitor (OEM)
provides a single-ended
buffered output for observing the equalized eye pattern. The
OEM output is a low impedance high-speed voltage driver
capable of driving an AC-coupled 100
load.
DS100056-20
FIGURE 1. CLC014 Equalizer Application Circuit
DS100056-21
FIGURE 2. CLC014 Block Diagram
C
www.national.com
8
相關(guān)PDF資料
PDF描述
CLC016ACQ Data Retiming PLL with Automatic Rate Selection
CLC016AJQ Data Retiming PLL with Automatic Rate Selection
CLC016 Data Retiming PLL with Automatic Rate Selection(帶自動(dòng)速率選擇的數(shù)據(jù)重定時(shí)PLL)
CLC018AJVJQ Circular Connector; No. of Contacts:41; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:20-41 RoHS Compliant: No
CLC018 8 x 8 Digital Crosspoint Switch, 1.4 Gbps(8 x 8數(shù)字交點(diǎn)開關(guān)，1.4 Gbps)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CLC014_03 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Adaptive Cable Equalizer for High-Speed Data Recovery
CLC014AJE 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述:IC CABLE EQUALIZER HI SPEED SMD 制造商:Texas Instruments 功能描述:IC, ADAPTIVE CABLE EQUALIZER, SOIC-14, IC Function:Adaptive Cable Equalizer, Bri
CLC014AJE/NOPB 功能描述:IC CABLE EQUALIZER ADAPTV 14SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
CLC014AJE/NOPB 制造商:Texas Instruments 功能描述:Buffer / Driver / Receiver Logic IC
CLC014AJE-TR13/NOPB 功能描述:IC CABLE EQUALIZER ADAPT 14-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*