參數(shù)資料
型號: CLC014
廠商: National Semiconductor Corporation
英文描述: Adaptive Cable Equalizer for High-Speed Data Recovery(應(yīng)用于高速數(shù)據(jù)恢復(fù)的可調(diào)電纜均衡器)
中文描述: 高自適應(yīng)電纜均衡器高速數(shù)據(jù)恢復(fù)(應(yīng)用于高速數(shù)據(jù)恢復(fù)的可調(diào)電纜均衡器)
文件頁數(shù): 11/18頁
文件大小: 519K
代理商: CLC014
Layout and Measurement
The printed circuit board layout for the CLC014 requires
proper high-speed layout to achieve the performance speci-
fications found in the datasheet. The following list contains a
few rules to follow:
1.
Use a ground plane.
2.
Decouple power pins with 0.1 μF capacitors placed
0.1” (3mm) from the power pins.
3.
Design transmission strip lines from the CLC014’s input
and output pins to the board connectors.
4.
Route outputs away from inputs.
5.
Keep ground plane
0.025” (0.06mm) away from the in-
put and output pads.
Figure 8 shows a block level measurement diagram, while
Figure 15on depicts a detailed schematic.Apseudo-random
pattern generator with low output jitter was used to provide a
NRZI pattern to create the eye diagrams shown in the
Typi-
cal Performance Characteristics
section.
Since most pattern generators have a 50
output imped-
ance, a translation can be accomplished using a CLC006
Cable Driver as an impedance transformer. A wide band-
width oscilloscope is needed to observe the high data rate
eye pattern. When monitoring a single output that is termi-
nated at both the equalizer output and the oscilloscope, the
effective output load is 37.5
. Consequently, the signal
swing is half that observed for a single-ended 75
termination.
Troubleshooting with scope probes can affect the equaliza-
tion. For high data rates, use a
low capacitance probe
with
less than 2 pF probe capacitance. Evaluation boards and lit-
erature are available for quick prototyping and evaluation of
the CLC014 Adaptive Cable Equalizer. The CLC014 con-
tains CMOS devices and operators should
use grounding
straps when handling
the parts.
Figure 9 shows the CLC014’s internal power supply routing.
Bypass V
CC
(pin 4) by:
Monolithic capacitor of about 0.1 μF placed less than 0.1”
(3mm) from the pin
Tantalum capacitor of about 6.8 μF for large current sig-
nal swings placed as close as convenient to the CLC014
To minimize ringing at the CLC014’s inputs, place a 100
re-
sistor in series with the input. This resistor reduces induc-
tance effects.
Several layout techniques can improve high speed perfor-
mance:
Keep input, output and AEC traces well separated
Use balanced input termination’s
Avoid routing traces close to the CLC014’s input trace
DS100056-28
FIGURE 8. Typical Measurement Block
DS100056-29
FIGURE 9. Power Package Routing Fixture
C
www.national.com
11
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