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參數(shù)資料
| 型號： | CH7202 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MPEG to TV Encoder with 8-bit Input |
| 中文描述： | 電視的MPEG編碼器8位輸入 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 110K |
| 代理商： | CH7202 |
CHRONTEL
CH7202
4
201-0000-030 Rev 2.0, 6/2/99
Table 2. Pin Descriptions (continued)
Pin
Type
Symbol
Description
26
In
M/S*
Master/Slave*
Internally pulled-up.
M/S*=1 then the CH7202 operates in master mode.
M/S*=0, then the CH7202 operates in slave mode.
19-25
In
NC
No Connect
28
In
RSET
Reference Resistor
A 360
resistor with short and wide traces should be attached
between RSET and ground. No other connections should be
made to this pin.
30
Out
C
Chrominance Output
A 75
termination resistor with short traces should be attached
between C and ground for optimum performance.
31
Out
CVBS
Composite Output
A 75
termination resistor with short traces should be attached
between CVBS and ground for optimum performance.
32
Out
Y
Luminance Output
A 75
termination resistor with short traces should be attached
between Y and ground for optimum performance.
33, 34, 40, 44
Power
GND
Digital Ground
These pins provide the ground reference for the digital section of
the CH7202. These pins MUST be connected to the system
ground through
independent
ground vias.
35
In/Out
HSYNC*
Horizontal Sync Input/Output
The horizontal sync output is generated by the CH7202 for master
mode operation. HSYNC* is an active low signal. In slave mode,
the horizontal sync becomes an input. For additional information,
please refer to the timing diagrams shown in
Figures 6
and
7
on
page 8.
37
In/Out
VSYNC*
Vertical Sync Input/Output
The vertical sync output is generated by the CH7202 for master
mode operation. VSYNC* is an active low signal. In slave mode,
the vertical sync becomes an input. For additional information,
please refer to the timing diagrams shown in
Figures 6
and
7
on
page 8.
38
In
MOD0
Mode bit 0
- internally pulled-up
This input works in conjunction with the MOD1 input to select
NTSC, PAL, or Sleep Mode functions. Refer to
Table 3, “Video
Encoder Modes,” on page 6
for details.
39
Out
PCLK
Video Pixel Clock Output
13.5 MHz clock output.
41
Out
DCLK
MPEG Decoder Clock Output
40.5 MHz or 33.9 MHz clock output (selectable by FS).
43
In/Out
2XPCLK
Double Pixel Clock Input/Output
27 MHz clock output. In slave mode, this pin becomes a 27 MHz
clock input.
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