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參數(shù)資料
| 型號： | CH7202 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MPEG to TV Encoder with 8-bit Input |
| 中文描述： | 電視的MPEG編碼器8位輸入 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 110K |
| 代理商： | CH7202 |
CHRONTEL
CH7202
201-0000-030 Rev 2.0, 6/2/99
3
Note:
required only if the crystal oscillation frequency cannot be controlled to the required accuracy. The capacitance value for the tuning capac-
itor should be obtained from the crystal manufacturer. For further information, request a copy of
Application Note AN-19, “Tuning Clock
Outputs.”
1.
Please refer to crystal manufacturer specifications for proper load capacitances. The optional variable tuning capacitor is
Table 1. Pin Descriptions
Pin
Type
Symbol
Description
1
Out
ACLK
Audio Decoder Clock Output
16.934 MHz or 11.289 MHz clock output (selectable by FS) for
MPEG audio decoder operation. The output swing is 5V.
2, 36, 42
Power
VDD
Digital Supply Voltage
These pins supply the 5V power to the digital section of the
CH7202.
3
In
XO/FIN
Crystal Output or External F
REF
Input
1
A parallel resonance 14.31818 MHz (±
50 ppm) crystal may be
attached between XO/FIN and XI. An external CMOS compatible
clock can be connected to XO/FIN as an alternative.
Crystal Input
1
A parallel resonance 14.31818 MHz (±
50 ppm) crystal should be
attached between XI and XO/FIN. However, if an external CMOS
clock is attached to XO/FIN, XI should be connected to ground.
4
In
XI
5, 27
Power
AGND
Analog ground
These pins provide the ground reference for the analog section of
the CH7202. These pins MUST be connected to the system
ground to prevent latchup.
6,29
Power
AVDD
Analog Supply Voltage
These pins supply the 5V power to the analog section of the
CH7202.
7
In
YCSWAP
Luma/Chroma Swap.
Internally pulled-up.
YCSWAP=0 indicates a luminance sample is the first sample
following the leading edge of HSYNC*. YCSWAP=1 indicates a
chroma sample (Cb or CR depending on CbSWAP) is the first
sample following the leading edge of HSYNC*. See
Figure 5
on
page 7.
Frequency Select.
Internally pulled-up
FS = 1 (default), then DCLK = 40.5 MHz, ACLK = 16.934 MHz
FS = 0, then DCLK = 33.9 MHz, ACLK = 11.289 MHz
8
In
FS
9
In
MOD1
Mode bit 1 -
Internally pulled-up
This input works in conjunction with the MOD0 input to select
NTSC, PAL, or Sleep mode functions. Refer to
Table 3, “Video
Encoder Modes,” on page 6
for details.
10
In
CbSWAP
Cb/Cr Swap.
Internally pulled-up
When CbSWAP=0, the first chroma sample following the leading
edge of HSYNC* will be a Cb sample. When CbSWAP=1, the first
chroma sample following the leading edge of HSYNC* will be a Cr
sample. See
Figure 5
on page 7
11 – 18
In
YC[7:0]
Video Input
These pins accept the YCrCb data in CCIR656 (4:2:2) digital
video format. The sequence of the Y, Cb, Cr data is defined by
the YCSWAP and CbSWAP pins. For more details, please refer
to the timing diagram shown in
Figure 5
on page 7.
Y has a nominal range of 16–235.
Cb & Cr have a nominal range of 16–240, with 128 equal to zero.
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