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參數(shù)資料
| 型號： | CDP68HC68S1 |
| 廠商： | Intersil Corporation |
| 英文描述： | Serial Multiplexed Bus Interface(串行多路總線接口) |
| 中文描述： | 復(fù)用串行總線接口（串行多路總線接口） |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 72K |
| 代理商： | CDP68HC68S1 |
6-93
CDP68HC68S1
FIGURE 8. GENERAL MESSAGE PROCESSING.
ANY MESSAGES TO TRANSMIT
TRANSMIT THE MSG ID BYTE.
HAS THE MSG ID BEEN
RECEIVED FROM THE BUS
DOES THE REC’D MSG ID EQUAL
THE TRANSMITTED MSG ID
ARE THERE ANY MORE
MESSAGE BYTES TO TRANSMIT
TRANSMIT THE NEXT MSG
ID BYTE.
HAS THE BYTE BEEN
REC’D FROM THE BUS
DOES THE REC’D BYTE EQUAL
THE TRANSMITTED BYTE
ANY MSG ID RECEIVED
IS IDLE LOW
IS THIS MESSAGE OF
INTEREST TO US
SAVE THE RECEIVED BYTE.
HAS THE NEXT BYTE
BEEN RECEIVED YET
IS IDLE LOW
PROCESS THE MESSAGE.
“TRANSMIT” AN END OF MESSAGE CONDITION.
ABORT THIS MESSAGE
TRANSMISSION
DUE TO A COLLISION.
YES
NO
NO
YES = SEND REST OF MESSAGE
YES = WON BUS ARB.
YES
YES = ATTEMPT TO WIN BUS
ARBITRATION
YES
NO
NO
NO
YES = REC. A MSG
YES
NO
YES
(START)
NO
NO = LOST
NO
NO
YES
NO
YES
the arbitration-winning MCU) is of any interest. If so, it
should save the incoming message (the length of which may
be specified in the ID byte) and then wait for the IDLE line to
go high before re-attempting transmission (if still desired).
The flowchart in Figure 8 reflects this procedure.
The SCl Mode, Hardware
In the SCl mode, the TxD and RxD pins on the user micro-
computer must be connected to the XMlT and REC pins on
the SBlC chip, respectively, as shown in Figure 9. The
MCU’s SCl port should be configured for the same baud rate
and character format as that used by the bus interface (i.e. 1
start bit, 8 data bits and 1 stop bit). The start and stop bits
are used to synchronize the data, a byte transfers between
the user microcomputer and the SBl chip. When using the
SCl mode, the SBl chip should always be properly mode and
chip selected. This can be accomplished by either a user
microcomputer output signal or by permanent wiring. This is
required in order to always be able to receive messages
from other microcomputers on the bus, which can happen at
random. For the SCl mode, the SBl chip’s MODE pin must
be set to1 and the CS pin to 1.
SCI Mode, Software
The procedure to follow for transmitting/receiving in the SCI
mode is basically identical to that stated in the “Using the
CDP68HC68S1-Software” section above, with the following
exception:
Start of Message Delay
Transmitting a byte via the 68HC05 SCl port basically requires
loading the byte into the MCU’s SCl data register (once the SCI
port is initialized). However, after the SBlC’s IDLE pin drops
low, the user may have to create a delay before transmitting the
FIRST byte of a message; this necessary 2-bit time (256 inter-
nal clock periods) delay is called the Start of Message (SOM)
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相關(guān)代理商/技術(shù)參數(shù) |
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| CDP68HC68S1E | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Serial Multiplexed Bus Interface |
| CDP68HC68S1M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Serial Multiplexed Bus Interface |
| CDP68HC68T WAF | 制造商:Harris Corporation 功能描述: |
| CDP68HC68T1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control |
| CDP68HC68T1_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control |
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