參數(shù)資料
型號(hào)： CDP68HC68A2M
廠商： INTERSIL CORP
元件分類： ADC
英文描述： CMOS Serial 10-Bit A/D Converter
中文描述： 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝： PLASTIC, SOIC-20
文件頁(yè)數(shù)： 5/24頁(yè)
文件大?。?/td> 139K
代理商： CDP68HC68A2M
5
TABLE 1. CLOCK/CALENDAR AND ALARM DATA MODES
ADDRESS LOCATION
(H)
FUNCTION
DECIMAL RANGE
BCD DATA RANGE
(NOTE 4)
BCD DATE EXAMPLE
20
Seconds
0-59
00-59
18
21
Minutes
0-59
00-59
49
22
Hours
12 Hour Mode
(Note 5)
1-12
81-92 (AM)
A1-B2 (PM)
A3
Hours
24 Hour Mode
0-23
00-23
15
23
Day of the Week
(Sunday = 1)
1-7
01-07
03
24
Day of the Month
(Date)
1-31
01-31
29
25
Month
Jan = 1, Dec = 12
1-12
01-12
10
26
Years
0-99
00-99
85
28
Alarm Seconds
0-59
00-59
18
29
Alarm Minutes
0-59
00-59
49
2A
Alarm Hours (Note 6)
12 Hour Mode
1-12
01-12 (AM)
21-32 (PM)
23
Alarm Hours
24 Hour Mode
0-23
00-23
15
NOTES:
4. Example: 3:49:18, Tuesday. Oct. 29,1985.
5. Most significant Bit, D7, is “0” for 24 hours, and “1” for 12 hour mode. Data Bit D5 is “1” for P.M. and ‘0” for A.M. in 12 hour mode.
6. Alarm hours. Data Bit D5 is “1” for P.M. and “0” for A.M. in 12 hour mode. Data Bits D7 and D6 are DON’T CARE.
SECONDS
MINUTES
HOURS
DAY OF WEEK
DATE
MONTH
YEARS
NOT USED
SEC ALARM
MIN ALARM
HRS ALARM
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
STATUS REGISTER
CONTROL REGISTER
INTERRUPT CONTROL REGISTER
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
$30
$31
$32
CLOCK/CALENDAR
13 BYTES UNUSED
TEST MODE
32 RAM LOCATIONS
$00
$1F
$20
$32
$33
$3F
$55
85
63
51
50
32
31
0
R = READABLE
W = WRITABLE
R, W
R, W
R, W
R, W
R, W
R, W
R, W
W
W
W
R
R, W
R, W
FIGURE 2. ADDRESS MAP
CDP68HC68T1
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