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參數(shù)資料
| 型號： | CDP68HC68A2M |
| 廠商： | INTERSIL CORP |
| 元件分類： | ADC |
| 英文描述： | CMOS Serial 10-Bit A/D Converter |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 139K |
| 代理商： | CDP68HC68A2M |
18
NOTE: Example of a system in which the power is controlled by an external source. The LINE input pin can sense when the switch opens by use
of the POWER-SENSE INTERRUPT. The CDP68HC68T1 crystal drives the clock input to the CPU using the CLK OUT pin. On power down when
V
SYS
< V
BATT
+ 0.7V. V
BATT
will power the CDP68HC68T1. A threshold detect activates a P-Channel switch, connecting V
BATT
to V
DD
. V
BATT
always supplies power to the oscillator, keeping voltage frequency variation to a minimum.
FIGURE 17. EXTERNALLY CONTROLLED POWER SYSTEM DIAGRAM
A Procedure for Power-Down Operation might consist of the following:
1. Set power sense operation by writing bit 5 high in the Interrupt Control Register.
2. When an interrupt occurs, the CPU reads the Status Register to determine the interrupt source.
3. Sensing a power failure, the CPU does the necessary housekeeping to prepare for shutdown.
4. The CPU reads the Status Register again after several milliseconds to determine validity of power failure.
5. The CPU sets power-down bit 6 and disables all interrupts in the Interrupt Control Register when power down is verified. This
causes the CPU reset and clock out to be held low and disconnects the serial interface.
6. When power returns and V
SYS
rises above V
BATT
, power down is terminated. The CPU reset is released and serial communi-
cation is established.
System Diagrams
(Continued)
POR
V
SYS
V
DD
LINE
CDP68HC68T1
CE
CPUR
MISO
MOSI
SCK
V
BATT
CLK OUT
INT
V
DD
CDP68HC05C8B
PORT (e.g., PCO)
MISO
MOSI
SCK
RESET
OSC 1
IRQ
BRIDGE
GENERATOR
AC
LINE
V
DD
V
DD
CDP68HC68T1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP68HC68P1 | CMOS Serial 8-Bit Input/Output Port |
| CDP68HC68P1E | CMOS Serial 8-Bit Input/Output Port |
| CDP68HC68P1M | CMOS Serial 8-Bit Input/Output Port |
| CDP68HC68S1E | Serial Multiplexed Bus Interface |
| CDP68HC68S1M | Serial Multiplexed Bus Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP68HC68A2M96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial 10-Bit A/D Converter |
| CDP68HC68P1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial 8-Bit Input/Output Port |
| CDP68HC68P1D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| CDP68HC68P1E | 制造商:MISCELLANEOUS 功能描述: |
| CDP68HC68P1M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial 8-Bit Input/Output Port |
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