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參數(shù)資料
| 型號： | CDP1877E |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 中斷控制器 |
| 英文描述： | Programmable Interrupt Controller (PIC) |
| 中文描述： | CDP1800 SERIES COMPATIBLE, INTERRUPT CONTROLLER, PDIP28 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 45K |
| 代理商： | CDP1877E |
4-87
Second (High-Order Address) Byte
This byte is the High-Order vector Address that was written
into the PIC’s Page Register by the user. The PIC does not
alter this value in any way.
High-Order Vector Address
Third (Low-Order Address) Bytes
Bits indicated by A
X
(x = 4 to 7) are the same as pro-
grammed into the control register. All other bits are
generated by the PIC.
REGISTER ADDRESSES
In order to read/write or obtain an interrupt vector from any
PIC in the system, all chip selects (CS/A
X
, CS/A
Y
, CS, CS)
must be valid during TPA.
CS/A
X
and CS/A
Y
are multiplexed addresses; both must be
high during TPA, and set according to this table during TPB
to access the proper register.
BUS 7
BUS 0
A15
A14
A13
A12
A11
A10
A9
A8
INTERVAL 2
BUS 7
BUS 0
A7
A6
A5
A4
0
INTERVAL 4
BUS 7
BUS 0
A7
A6
A5
0
0
INTERVAL 8
BUS 7
BUS 0
A7
A6
0
0
0
INTERVAL 16
BUS 7
BUS 0
A7
0
0
0
0
Indicates active interrupt input number (binary 0 to 7).
I2
I1
I0
I2
I1
I0
I2
I1
I0
I2
I1
I0
CS/A
X
CS/A
Y
RD
WR
ACTION TAKEN
1
0
0
1
READ Long Branch instruction and vector for highest
priority unmasked interrupt pending.
1
0
1
0
WRITE to Page Register
0
1
1
0
WRITE to Control Register
0
0
0
1
READ Status Register
0
0
1
0
WRITE to Mask Register
0
1
0
1
READ Polling Register (Used to identify INTERRUPT
source if Polling technique rather than INTERRUPT ser-
vice is used.)
1
1
X
X
Unused condition
CDP1877, CDP1877C
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