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參數(shù)資料
| 型號： | CDP1877E |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 中斷控制器 |
| 英文描述： | Programmable Interrupt Controller (PIC) |
| 中文描述： | CDP1800 SERIES COMPATIBLE, INTERRUPT CONTROLLER, PDIP28 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 45K |
| 代理商： | CDP1877E |
4-86
The Low Order Vector Address will be set according to the table below:
Mask Register
A ”1” written into any location in this write only register will
mask the corresponding interrupt request line. All interrupt
inputs (except CASCADE) are maskable.
Status Register
In this read only register a “1” will be present in the
corresponding bit location for every masked or unmasked
pending interrupt.
Polling Register
This read only register provides the low order vector address
and is used to identify the source of interrupt if a polling
technique, rather than interrupt servicing, is used.
RESPONSE TO INTERRUPT (AFTER S3 CYCLE)
The PIC’s response to interrogation by the CPU is always 3
bytes long, placed on the data bus in consecutive bytes in
the following format:
First (Instruction) Byte:
LONG BRANCH INSTRUCTION - CO (Hex)
INTERVAL SELECTED NO. OF BYTES
LOW ADDRESS BITS
BIT B7
BIT B6
BIT B5
BIT B4
2
SETS A7
SETS A6
SETS A5
SET A4
4
SETS A7
SETS A6
SETS A5
X
8
SETS A7
SETS A6
X
X
16
SETS A7
X
X
X
NOTES:
1. X = Don’t Care
2. All Don’t Care addresses and addresses A0-A3 are determined by interrupt request.
BUS 7
BUS 0
MASK REGISTER BITS
M4
WRITE ONLY
M7
M6
M5
M3
M2
M1
M0
BUS 7
BUS 0
STATUS REGISTER BITS
S4
READ ONLY
S7
S6
S5
S3
S2
S1
S0
BUS 7
BUS 0
POLLING REGISTER BITS
P4
READ ONLY
P7
P6
P5
P3
P2
P1
P0
BUS 7
BUS 0
1
1
0
0
0
0
0
0
CDP1877, CDP1877C
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