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參數(shù)資料
| 型號： | CDP1855E |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | 8-Bit Programmable Multiply/Divide Unit |
| 中文描述： | 3-BIT, DSP-MULTIPLIER, PDIP28 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 85K |
| 代理商： | CDP1855E |
4-55
The result of 201F7C
16
x 723C09
16
is 0E558DBA2B5C =
15760612797276
10
. It will be stored in memory as follows:
0010
653C;
0017
OUT 5;
DC 030H
. . LOAD NEXT MSB OF Z REG
0012
;
0018
. . WITH 3C
0012
6509;
0019
OUT 5;
DC 09H
. . LOAD LSB OF Z REGISTER
0014
;
0020
. . WITH 09
0014
6759;
0021
OUT 7;
DC 059H
. . LOAD CONTROL REGISTERS
0016
;
0022
. . RESETTING Y REGISTERS
0016
;
0023
. . AND SEQUENCE COUNTERS
0016
;
0024
. . AND STARTING MULTIPLY
0016
;
0025
. . OPERATION
DELAY FOR MULTIPLY TO FINISH
0016
E2;
0026
SEX R2
0017
6E60;
0027
INP 6;
IRX
. . MSB OF RESULTS IS STORED
0019
;
0028
. . AT LOCATION 0030
0019
6E60;
0029
INP 6;
IRX
001B
6E60;
0030
INP 6;
IRX
001D
6D60;
0031
INP 5;
IRX
001F
6D60;
0032
INP 5;
IRX
0021
6D;
0033
INP 5
. . COMPLETE LOADING RESULT
0022
;
0034
. . INTO MEMORY LOCATIONS
0022
;
0035
. . 0030 TO 0035
0022
;
0036
. . RESULTS = 0E558DBA2B5C
0022
3022;
0037 STOP
BR STOP
0024
;
0038
END
0000
Programming Example for Multiplication
For a 24-bit x 24-bit multiply using the system shown in Figure 5, the following is an assembly listing of a program to multiply 201F7C
16
by
723C09
16
:
(Continued)
MEMORY
LOCATION
OP
CODE
LINE
NO.
ASSEMBLY LANGUAGE
LOC
BYTE
0030
0E
31
55
32
8D
33
BA
34
2B
35
5C
BEFORE MULTIPLY
MDU1
MDU2
MDU3
REGISTER X
20
1F
7C
REGISTER Y
00
00
00
REGISTER Z
72
3C
09
AFTER MULTIPLY
MDU1
MDU2
MDU3
REGISTER X
20
1F
7C
REGISTER Y
0E
55
8D
REGISTER Z
BA
2B
5C
CDP1855, CDP1855C
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