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參數(shù)資料
| 型號(hào)： | CDP1855E |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | 8-Bit Programmable Multiply/Divide Unit |
| 中文描述： | 3-BIT, DSP-MULTIPLIER, PDIP28 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大小： | 85K |
| 代理商： | CDP1855E |
4-54
CDP1855 Interfacing Schemes
FIGURE 3. REQUIRED CONNECTION FOR MEMORY MAPPED
ADDRESSING OF THE MDU
FIGURE 4. INTERFACING THE CDP1855 TO AN 8085 MICRO-
PROCESSOR AS AN I/O DEVICE
Programming Example for Multiplication
For a 24-bit x 24-bit multiply using the system shown in Figure 5, the following is an assembly listing of a program to multiply 201F7C
16
by
723C09
16
:
MEMORY
LOCATION
OP
CODE
LINE
NO.
ASSEMBLY LANGUAGE
0000
F830;
0001
LDI 030H
0002
A2;
0002
PLO R2
. . LOAD 30 INTO R2.0
0003
F800;
0003
LDI 00H
0005
B2;
0004
PHI R2
. . LOAD 00 INTO R2.1 (R2=0030)
0006
6758;
0005
OUT 7;
DC 058H
. . LOAD CONTROL REGISTERS
0008
;
0006
. . SPECIFYING THREE MDU’s
0008
;
0007
. . RESET THE Y REGISTER AND
0008
;
0008
. . SEQUENCE COUNTER
0008
6420;
0009
OUT 4;
DC 020H
. . LOAD MSB OF X REGISTER
000A
;
0010
. . WITH 20
000A
641F;
0011
OUT 4;
DC 01FH
. . LOAD NEXT MSB OF X REG
000C
;
0012
. . WITH 1F
000C
647C;
0013
OUT 4;
DC 07CH
. . LOAD LSB OF X REGISTER
000E
;
0014
. . WITH 7C
000E
6572;
0015
OUT 5;
DC 072H
. . LOAD MSB OF Z REGISTER
0010
;
0016
. . WITH 72
CLEAR
XTAL
MA0
MA1
MAX
TPA
MWR
MRD
TPB
EF
BUS
HIGH
ADDRESS
LATCH
CDP1802
CLEAR
CLOCK
RA0
RA1
CI
CN0
CN1
Y
L
Z
R
CTL
Y
R
Z
L
BUS
CDP1855
RE/WE
CE
STB
CO
RA2
+V
DD
CI
BUS 0
CE
15
BUS 1
16
BUS 2
17
BUS 3
18
BUS 4
19
BUS 5
20
BUS 6
21
BUS 7
22
Z
R
23
Y
L
5
CTL
3
Z
L
6
Y
R
24
RA0
RA1
RA2
1
13
12
11
STB
RD/WE
CLK
CLEAR
9
10
8
2
CN1
CN0
V
DD
V
SS
25
26
27
28
14
A8
A9
IO/M
WR
CLK (OUT)
RD
DATA BUS
DATA
BUS
RESET OUT
1/4 CD4011
1/4 CD4011
V
CC
8
CDP1855
MDU
CDP1855, CDP1855C
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