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參數(shù)資料
| 型號： | CDP1852 |
| 廠商： | Intersil Corporation |
| 英文描述： | parallel, 8-bit, mode-pro-grammable input/output ports.(并行8位可編程模式I/O端口) |
| 中文描述： | 同時，8位，模式親可編程輸入/輸出端口。（并行8位可編程模式的I / O端口） |
| 文件頁數(shù)： | 9/9頁 |
| 文件大小： | 63K |
| 代理商： | CDP1852 |
4-27
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Application Information
In a CDP1800 series microprocessor-based system where
MRD is used to distinguish between INP and OUT
instructions, an lNP instruction is assumed to occur at the
beginning of every I/O cycle because MRD starts high.
Therefore, at the start of an OUT instruction, which uses the
same 3-bit N code as that used for selection of an input port,
the input device is selected for a short time (see Figure 8).
This condition forces SR low and sets the internal SR latch
(see Figure 3). In a small system with unique N codes for
inputs and outputs, this situation does not arise. Using the
CDP1853 N-bit decoder or equivalent logic to decode the N
lines after TPA prevents dual selection in larger systems
(see Figure 9 and Figure 10).
FIGURE 8. EXECUTION OF A “65” OUTPUT INSTRUCTION SHOWING MOMENTARY SELECTION OF INPUT PORT “D”
FIGURE 9. CDP1853 TIMING WAVEFORMS
NOTE:
1. Output enabled when EN = HIGH. Internal signal shown for refer-
ence only (See Figure 1).
FIGURE10. CDP1853 FUNCTIONAL DIAGRAM
MRD
SR
SELECT
N2
N1
N0
6D
65
TPA
TPB
CE
EN
OUTPUT
(NOTE 1)
4
5
6
7
12
11
10
9
OUT 7
OUT 6
OUT 5
OUT 4
OUT 3
OUT 2
OUT 1
1 OF 8
DECODER
N0
N1
N2
2
3
14
EN
CE
13
CLOCK A
(TPA)
CLOCK B
(TPB)
1
15
Qn
OUT 0
CDP1852, CDP1852C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1852C | parallel, 8-bit, mode-pro-grammable input/output ports.(并行8位可編程模式I/O端口) |
| CDP1853C | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853CD3 | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853 | N-Bit 1 of 8 Decoder |
| CDP1853CD | N-Bit 1 of 8 Decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1852 DIE | 制造商:Harris Corporation 功能描述: |
| CDP1852/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
| CDP18523 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
| CDP1852C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Byte-Wide Input/Output Port |
| CDP1852C/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
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