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參數(shù)資料
| 型號： | CDP1852 |
| 廠商： | Intersil Corporation |
| 英文描述： | parallel, 8-bit, mode-pro-grammable input/output ports.(并行8位可編程模式I/O端口) |
| 中文描述： | 同時，8位，模式親可編程輸入/輸出端口。（并行8位可編程模式的I / O端口） |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 63K |
| 代理商： | CDP1852 |
4-24
FIGURE 4. MODE 0 INPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
FIGURE 5. INPUT PORT MODE 0 FUNCTIONAL DIAGRAM AND WAVEFORMS - TYPICAL OPERATION
t
WW
t
SW
t
DH
t
DS
t
SDO
t
DOH
t
SSR
t
CSR
t
RSR
t
CLR
HIGH
IMPEDANCE
DATA BUS
SR
CLEAR
DATA IN
CLOCK
CS1 - CS2
(NOTE 1)
MODE 0 TRUTH TABLE
CLOCK
CS1-CS2
CLEAR
DATA OUT EQUALS
X
0
X
High Impedance
0
1
0
0
0
1
1
Data Latch
1
1
X
Data In
CS1
CS2: CS1 = 1, CS2 = 1
SERVICE REQUEST TRUTH TABLE
CLOCK
CS1 or CS2
or CLEAR
SR/SR
0
SR/SR
1
NOTE 1. CS1
CS2 is the overlap of CS1 = 1 and CS2 = 1.
CS2
CDP1852
DATA BUS
CS1
SR
MODE
D0
D1
CLOCK
STROBE
DATA FROM
PERIPHERAL
V
SS
CDP1802
MRD
N
X
MEMORY
ADDRESS
LINES
EF
X
PERIPHERAL DEVICE
PLACES DATA IN CDP1852
AND CDP1852 SIGNALS
CDP1802 THAT DATA IS READY
VALID
THREE - STATE
DATA BUS
MRD
N
X
SR/SR
PERIPHERAL
STROBE
DATA
CDP1802 SELECTS
CDP1852 AND DATA
IS TRANSFERRED
TO MEMORY AND
THE MICROPROCESSOR
CDP1852, CDP1852C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1852C | parallel, 8-bit, mode-pro-grammable input/output ports.(并行8位可編程模式I/O端口) |
| CDP1853C | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853CD3 | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853 | N-Bit 1 of 8 Decoder |
| CDP1853CD | N-Bit 1 of 8 Decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1852 DIE | 制造商:Harris Corporation 功能描述: |
| CDP1852/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
| CDP18523 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
| CDP1852C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Byte-Wide Input/Output Port |
| CDP1852C/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
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