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參數(shù)資料
| 型號(hào)： | CDP1852 |
| 廠商： | Intersil Corporation |
| 英文描述： | parallel, 8-bit, mode-pro-grammable input/output ports.(并行8位可編程模式I/O端口) |
| 中文描述： | 同時(shí)，8位，模式親可編程輸入/輸出端口。（并行8位可編程模式的I / O端口） |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 63K |
| 代理商： | CDP1852 |
4-25
Output Port Mode 1 - Typical Operation
General Operation
Connecting the mode control to V
DD
configures the
CDP1852 as an output port. The output drivers are always
on in this mode, so any data in the 8-bit register will be
present at the data-out lines when the CDP1852 is selected.
The N line and MRD connections between the CDP1852
and CDP1802 remain the same as in the input mode
configuration, but now the clock input of the CDP1852 is tied
to the TPB output of the CDP1802 and the SR output of the
CDP1852 will be used to signal the peripheral device that
valid data is present on its input lines. The microprocessor
issues an output instruction, and data from the memory is
strobed into the CDP1852 with the TPB pulse. When the
CDP1852 is deselected, the SR output goes high to signal
the peripheral device.
Detailed Operation
(See Figure 7)
The CDP1802 issues an output instruction. The N
X
line goes
high and the MRD line goes low. The memory is accessed
M(R(X))
→
BUS and places data on the DATA BUS. This
data are strobed into the 8-bit register of the CDP1852 when
TPB goes high and latched on the TPB’s trailing edge. The
valid data thus appears on the CDP1852 output lines. When
the CDP1802 output instruction cycle is complete, the N
X
line goes low and the SR output goes high. SR will remain
high until the trailing edge of the next TPB pulse, when it will
return low.
Dynamic Electrical Specifications
At T
A
= -40
o
C to +85
o
C, V
DD
=
±
5%, t
R
, t
F
= 20ns, V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
, C
L
= 100pF,
and 1 TTL Load
PARAMETER
V
DD
(V)
LIMITS
UNITS
MIN
(NOTE 1)
TYP
MAX
MODE 1- OUTPUT PORT
(See Figure 6)
Minimum Clock Pulse Width
t
CLK
5
-
130
260
ns
10
-
65
130
ns
Minimum Write Pulse Width
t
WW
5
-
130
260
ns
10
-
65
130
ns
Minimum Clear Pulse Width
t
CLR
5
-
60
120
ns
10
-
30
60
ns
Minimum Data Setup Time
t
DS
5
-
-10
0
ns
10
-
-5
0
ns
Minimum Data Hold Time
t
DH
5
-
75
150
ns
10
-
35
75
ns
Minimum Select-After-Clock Hold Time
t
SH
5
-
-10
0
ns
10
-
-5
0
ns
Propagation Delay Times, t
PLH
, t
PHL
Clear to Data Out
t
RDO
5
-
140
280
ns
10
-
70
140
ns
Write to Data Out
t
WDO
5
-
220
440
ns
10
-
110
220
ns
Data In to Data Out
t
DDO
5
-
100
200
ns
10
-
50
100
ns
Clear to SR
t
RSR
5
-
120
240
ns
10
-
60
120
ns
Clock to SR
t
CSR
5
-
120
240
ns
10
-
60
120
ns
Select to SR
t
SSR
5
-
120
240
ns
10
-
60
120
ns
NOTE:
1. Typical values are for T
A
= 25
o
C and nominal V
DD
.
CDP1852, CDP1852C
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PDF描述 |
|---|---|
| CDP1852C | parallel, 8-bit, mode-pro-grammable input/output ports.(并行8位可編程模式I/O端口) |
| CDP1853C | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853CD3 | High-Reliability CMOS N-Bit 1 of 8 Decoder |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CDP1852 DIE | 制造商:Harris Corporation 功能描述: |
| CDP1852/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
| CDP18523 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
| CDP1852C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Byte-Wide Input/Output Port |
| CDP1852C/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
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