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參數(shù)資料
| 型號： | CDP1806ACEX |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| 中文描述： | 8-BIT, 5 MHz, MICROPROCESSOR, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 8/30頁 |
| 文件大小： | 301K |
| 代理商： | CDP1806ACEX |
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8
NOTES:
This Timing Diagram is used to show signal relationships only, and does not represent any specific machine cycle.
All measurements are referenced to 50% point of the wave forms.
Shaded areas indicate “don’t care” or undefined state. Multiple transitions may occur during this period.
For the run (RAM only) mode only.
For the run (RAM/ROM) mode only.
FIGURE 5. TIMING WAVEFORMS
00
01
10
11
20
21
30
31
40
41
50
51
60
61
70
0
71
00
01
1
2
3
4
5
6
7
0
t
W
CLOCK
t
PLH
t
PHL
TPA
t
PLH,
t
PHL
t
PLH
t
PHL
TPB
t
SU
t
PLH,
t
PHL
HIGH ORDER
ADDRESS BYTE
LOW ORDER
ADDRESS BYTE
t
H
MEMORY
ADDRESS
t
PLH
t
SU
t
PHL
t
PHL
MRD
(MEMORY
READ CYCLE)
MWR
(MEMORY
WRITE CYCLE)
t
PHL
t
PLH
ME
(MEMORY
ENABLE)
t
SU
IS ALLOWABLE
INTERNAL RAM
ACCESS TIME
t
SU
t
H
t
PHL
t
PLH
EMS
(EXTERNAL
MEMORY
SELECT)
t
PLH,
t
PHL
t
H
DATA FROM
CPU TO BUS
DATA FROM
INTERNAL MEMORY
TO BUS (ME = LOW)
t
PLH
t
PHL
t
PLH,
t
PLH
STATE CODES
t
PLH,
t
PHL
Q
N0, N1, N2
(I/O EXECUTION
CYCLE)
t
PLH
t
PHL
DATA LATCHED
IN CPU
t
SU
DATA FROM
BUS TO CPU
t
H
DMA SAMPLED (S1, S2, S3)
t
SU
DMA REQUEST
INTERRUPT
SAMPLED (S1, S2)
t
SU
t
H
INTERRUPT
REQUEST
EF1 - EF4
t
SU
t
H
WAIT
t
SU
t
H
t
SU
t
H
t
WL
CLEAR
t
H
t
PLH,
t
PHL
FLAG LINES
SAMPLED END OF S0
t
H
t
PLH,
t
PHL
CDP1805AC, CDP1806AC
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相關代理商/技術參數(shù) |
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|---|---|
| CDP1806ACQ | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
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