參數(shù)資料
型號(hào)： CDP1806ACE
廠商： INTERSIL CORP
元件分類： 微控制器/微處理器
英文描述： CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer
中文描述： 8-BIT, 5 MHz, MICROPROCESSOR, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 7/30頁(yè)
文件大小： 301K
代理商： CDP1806ACE
7
Timing Waveforms For Possible Operating Modes
NOTE:
8. ME has a minimum setup and hold time with respect to the beginning of clock 70. For a memory read operation, RAM data will appear on
the data bus during the time ME is active after clock 31. The time shown can be longer, if for instance, a DMA out operation is performed
on internal RAM data, to allow data enough time to be latched into an external device. The internal RAM is automatically deselected at
the end of clock 71 independent of ME.
For CDP1805AC only.
FIGURE 3. INTERNAL MEMORY OPERATION TIMING WAVEFORMS
NOTE:
For CDP1805AC only.
FIGURE 4. EXTERNAL MEMORY OPERATION TIMING WAVEFORMS
00
10
20
30
40
50
60
70
00
10
20
30
40
50
60
70
01
11
21
31
41
51
61
71
01
11
21
31
41
51
61
71
CLOCK
TPA
TPB
MEMORY
ADDRESS
MRD
MWR
ME
IN
DATA
BUS
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
VALID DATA FROM MEMORY
VALID DATA FROM CPU
INTERNAL RAM READ CYCLE
INTERNAL RAM WRITE CYCLE
00
10
20
30
40
50
60
70
00
10
20
30
40
50
60
70
CLOCK
TPA
TPB
MRD
MWR
ME IN
(HIGH)
DATA
BUS
01
11
21
31
41
51
61
71
01
11
21
31
41
51
61
71
MEMORY
ADDRESS
HIGH BYTE
LOW BYTE
LOW BYTE
HIGH BYTE
DATA LATCHED IN CPU
VALID DATA FROM CPU
EXTERNAL MEMORY READ CYCLE
EXTERNAL MEMORY WRITE CYCLE
CDP1805AC, CDP1806AC
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