- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379855 > CDP1806ACE (INTERSIL CORP) CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer PDF資料下載
參數(shù)資料
| 型號(hào)： | CDP1806ACE |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| 中文描述： | 8-BIT, 5 MHz, MICROPROCESSOR, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁(yè)數(shù)： | 17/30頁(yè) |
| 文件大小： | 301K |
| 代理商： | CDP1806ACE |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)
17
Instruction Set
The CDP1805AC and CDP1806AC instruction summary is
given in Table 1. Hexadecimal notation is used to refer to the
4-bit binary codes.
In all registers, bits are numbered from the least significant
bit (LSB) to the most significant bit (MSB) starting with 0.
R(W): Register designated by W, where
W = N or X, or P
R(W).0: Lower-order byte of R(W)
R(W).1: Higher-order byte of R(W)
Operation Notation
M (R(N))
→
D; R(N) + 1
→
R(N)
This notation means: The memory byte pointed to by R(N) is
loaded into D, and R(N) is incremented by 1.
TABLE 1. INSTRUCTION SUMMARY
(SEE NOTES)
INSTRUCTION
NO. OF
MACHINE
CYCLES
MNEMONIC
OP CODE
OPERATION
MEMORY REFERENCE
LOAD IMMEDIATE
2
LDI
F8
M(R(P))
→
D; R(P) + 1
→
R(P)
REGISTER LOAD IMMEDIATE
5
RLDI
68CN
(Note 10)
M(R(P))
→
R(N).1; M(R(P)) + 1
→
R(N).0; R(P) + 2
→
R(P)
LOAD VIA N
2
LDN
0N
M(R(N))
→
D; FOR N NOT 0
LOAD ADVANCE
2
LDA
4N
M(R(N))
→
D; R(N) + 1
→
R(N)
LOAD VIA X
2
LDX
F0
M(R(X))
→
D
LOAD VIA X AND ADVANCE
2
LDXA
72
M(R(X))
→
D; R(X) + 1
→
R(X)
REGISTER LOAD VIA X AND
ADVANCE
5
RLXA
686N
(Note 10)
M(R(X))
→
R(N).1; M(R(X) + 1)
→
R(N).0; R(X)) + 2
→
R(X)
STORE VIA N
2
STR
5N
D
→
M(RN))
STORE VIA X AND DECREMENT
2
STXD
73
D
→
M(R(X)); R(X) - 1
→
R(X)
REGISTER STORE VIA X AND
DECREMENT
5
RSXD
68AN
(Note 10)
R(N).0
→
M(R(X)); R(N).1
→
M(R)(X) - 1); R(X) - 2
→
R (X)
REGISTER OPERATIONS
INCREMENT REG N
2
INC
1N
R(N) + 1
→
R(N)
DECREMENT REG N
2
DEC
2N
R(N) - 1
→
R(N)
DECREMENT REG N AND LONG
BRANCH IF NOT EQUAL 0
5
DBNZ
682N
R(N) - 1
→
R(N); IF R(N) NOT 0,
M(R(P))
→
R(P).1, M(R(P) + 1)
→
R(P).0, ELSE R(P) + 2
→
R(P)
INCREMENT REG X
2
IRX
60
R(X) + 1
→
R(X)
GET LOW REG N
2
GLO
8N
R(N).0
→
D
PUT LOW REG N
2
PLO
AN
D
→
R(N).0
GET HIGH REG N
2
GHI
9N
R(N).1
→
D
PUT HIGH REG N
2
PHI
BN
D
→
R(N).1
REGISTER N TO REGISTER X
COPY
4
RNX
68BN
(Note 10)
R(N)
→
R(X)
LOGIC OPERATIONS
(Note 19)
OR
2
OR
F1
M(R(X)) OR D
→
D
OR IMMEDIATE
2
ORI
F9
M(R(P)) OR D
→
D; R(P) + 1
→
R(P)
EXCLUSIVE OR
2
XOR
F3
M(R(X)) XOR D
→
D
EXCLUSIVE OR IMMEDIATE
2
XRI
FB
M(R(P)) XOR D
→
D;
R(P) + 1
→
R(P)
AND
2
AND
F2
M(R(X)) AND D
→
D
CDP1805AC, CDP1806AC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1806ACEX | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1821C | High-Reliability CMOS 1024-Word x 1-Bit Static RAM |
| CDP1821C3 | High-Reliability CMOS 1024-Word x 1-Bit Static RAM |
| CDP1821CD3 | High-Reliability CMOS 1024-Word x 1-Bit Static RAM |
| CDP1822C | High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1806ACE114 | 制造商:Harris Corporation 功能描述: |
| CDP1806ACEX | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDP1806ACQ | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| CDP1821C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 1024-Word x 1-Bit Static RAM |
| CDP1821C/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 1024-Word x 1-Bit Static RAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。