參數(shù)資料
型號(hào)： CDCV850I
廠商： Texas Instruments, Inc.
英文描述： 2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2 LINE SERIAL INTERFACE
中文描述： 2.5 V的鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器，帶有2線串行接口
文件頁(yè)數(shù)： 7/15頁(yè)
文件大?。?/td> 228K
代理商： CDCV850I
SCAS647B OCTOBER 2000 REVISED DECEMBER 2002
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of operating free-air temperature (unless
otherwisw noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tpd
tPHL
ten
tdis
tjit(per)
tjit(cc)
tjit(hper)
Propagation delay time
Test mode/CLK to any output
4
ns
High-to low-level propagation delay time
SCLK to SDATA (acknowledge)
500
ns
Output enable time
Test mode/SDATA to Y-output
85
ns
Output disable time
Test mode/SDATA to Y-output
35
ns
Jitter (period), See Figure 6
100/133 MHz
30
30
ps
Jitter (cycle-to-cycle), See Figure 3
100/133 MHz
30
30
ps
Half-period jitter, See Figure 7
100/133 MHz
75
75
ps
100 MHz/VID on CLK = 0.71 V
120
120
0
°
C to 85
°
C
100 MHz/VID on CLK = 0.59 V
50
160
ps
100 MHz/VID on CLK = 0.82 V
170
70
t( )
Static phase offset, See Figure 4a
133 MHz/VID on CLK = 0.71 V
50
180
100 MHz/VID on CLK = 0.71 V
160
80
40
°
C to 85
°
C
100 MHz/VID on CLK = 0.59 V
90
120
ps
100 MHz/VID on CLK = 0.82 V
210
30
133 MHz/VID on CLK = 0.71 V
80
150
Dynamic phase offset, SSC on, See Figure 4b and
Figure 9
100 MHz/VID on CLK = 0.71 V
190
190
ps
td( )#
133 MHz/VID on CLK = 0.71 V
140
140
ps
Dynamic phase offset, SSC off, See Figure 4b
100 MHz/VID on CLK = 0.71 V
160
160
ps
133 MHz/VID on CLK = 0.71 V
130
130
ps
tslr(o)
Output clock slew rate, terminated with 120
/14 pF, See Figures 1 and 8
1
2
V/ns
tslr(o)
Output clock slew rate, terminated with 120
/4 pF, See Figures 1 and 8
1
3
V/ns
tsk(o)
Output skew, See Figure 5
75
ps
SSC modulation frequency
30
33.3
kHz
SSC clock input frequency deviation
This time is for a PLL frequency of 100 MHz.
According CK00 spec: 6 x Iref at 50
and Rref = 475
§According CK00 spec: 5 x Iref at 50
and Rref = 475
According CK00 spec: 7 x Iref at 50
and Rref = 475
#The parameter is assured by design but cannot be 100% production tested.
||All differential output pins are terminated with 120
/4 pF
0.00
0.50
%
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CDCV850IDGG 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 2.5V Ph Lock Loop Diff Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
CDCV850IDGGG4 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 2.5V Ph Lock Loop Diff Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
CDCV850IDGGR 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 2.5V Ph Lock Loop Diff Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
CDCV850IDGGRG4 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 2.5V Ph Lock Loop Diff Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
CDCV855 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.5-V PHASE-LOCK LOOP CLOCK DRIVER
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