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參數(shù)資料
| 型號： | CDCV850I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2 LINE SERIAL INTERFACE |
| 中文描述： | 2.5 V的鎖相環(huán)時鐘驅動器，帶有2線串行接口 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 228K |
| 代理商： | CDCV850I |
SCAS647B OCTOBER 2000 REVISED DECEMBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: V
DDQ,
AV
DD
0.5 V to 3.6 V
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
I
(except SCLK and SDATA) (see Notes 1 and 2)
V
I
(SCLK, SDATA) (see Notes 1 and 2)
Output voltage range: V
O
(except SDATA) (see Notes 1 and 2)
V
O
(SDATA) (see Notes 1 and 2)
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
DDQ
)
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
DDQ
)
Continuous output current, I
O
(V
O
= 0 to V
DDQ
)
Package thermal impedance,
θ
JA
(see Note 3): DGG package
Storage temperature range T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
V
DDI
Input voltage range:
–
0.5 V to V
DDQ
+ 0.5 V
–
0.5 V to V
DDI
+ 0.5 V
–
0.5 V to V
DDQ
+ 0.5 V
–
0.5 V to V
DDQ
+ 0.5 V
. . . . . . . .
. . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
50 mA
±
50 mA
±
50 mA
89
°
C/W
–
65
°
C to 150
°
C
MIN
2.3
TYP
MAX
UNIT
Supply voltage
VDDQ, AVDD
VDDI (see Note 5)
CLK, CLK, HCSL Buffer only
2.7
V
2.3
3.6
0
0.24
Low level input voltage, VIL
CLK, CLK
0.3
VDDQ 0.4
VDDQ/2 0.18
0.3
×
VDDI
V
FBIN, FBIN
SDATA, SCLK
CLK, CLK, HCSL Buffer only
0.66
0.71
High level input voltage, VIH
CLK, CLK
0.4
VDDQ + 0.3
V
FBIN, FBIN
VDDQ/2 + 0.18
0.7
×
VDDI
–0.3
SDATA, SCLK
DC input signal voltage (see Note 6)
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.55
×
(VIHVIL)
V
Differential input signal voltage, VID (see Note 7)
DC
AC
CLK, FBIN
0.36
V
CLK, FBIN
0.2
Input differential pair cross-voltage, VIX (see Note 8)
High-level output current, IOH
0.45
×
(VIHVIL)
V
12
mA
Low-level output current, IOL
12
V
SDATA
3
mA
Input slew rate, SR (see Figure 8)
1
4
V/ns
SSC modulation frequency
30
33.3
kHz
SSC clock input frequency deviation
0
0
0.50
kHz
Operating free-air temperature, TA
Commericial
85
°
C
Industrial
40
85
NOTES:
4. Unused inputs must be held high or low to prevent them from floating.
5. All devices on the serial interface bus, with input levels related to VDDI, must have one common supply line to which the pullup resistor
is connected to.
6. DC input signal voltage specifies the allowable dc execution of differential input.
7. Differential input signal voltage specifies the differential voltage |VTR VCP| required for switching, where VTR is the true input level
and VCP is the complementary input level.
8. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be
crossing.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CDCV850IDGG | 功能描述:時鐘驅動器及分配 2.5V Ph Lock Loop Diff Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCV850IDGGG4 | 功能描述:時鐘驅動器及分配 2.5V Ph Lock Loop Diff Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCV850IDGGR | 功能描述:時鐘驅動器及分配 2.5V Ph Lock Loop Diff Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCV850IDGGRG4 | 功能描述:時鐘驅動器及分配 2.5V Ph Lock Loop Diff Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCV855 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.5-V PHASE-LOCK LOOP CLOCK DRIVER |
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