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參數(shù)資料
| 型號： | CDCU2A877ZQL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1.8-V PHASE LOCK LOOP CLOCK DRIVER |
| 中文描述： | 的1.8 V鎖相環(huán)時鐘驅(qū)動器 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 362K |
| 代理商： | CDCU2A877ZQL |
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
(1)
CDCU2A877
SCAS827–AUGUST 2006
PARAMETER
TEST CONDITIONS
See
Figure 12
See
Figure 12
MIN
TYP
MAX
UNIT
ns
ns
t
en
t
dis
t
jit(cc+)
t
jit(cc-)
t
(
φ
)
t
(
φ
)dyn
t
sk(o)
Enable time, OE to any Y/Y
Disable time, OE to any Y/Y
8
8
0
0
40
–40
50
20
35
30
20
75
50
80
60
Cycle-to-cycle period jitter
(2)
160 MHz to 410 MHz, See
Figure 5
ps
Static phase offset time
(3)
Dynamic phase offset time,
(4)
Output clock skew
(4)
See
Figure 4
See
Figure 11
See
Figure 7
160 MHz to 270 MHz, See
Figure 8
271 MHz to 410 MHz, See
Figure 8
160 MHz to 270 MHz, See
Figure 9
271 MHz to 410 MHz, See
Figure 9
271 MHz to 410 MHz
271 MHz to 410 MHz
See
Figure 3
and
Figure 8
See
Figure 3
and
Figure 8
See
Figure 3
and
Figure 8
See
Figure 2
–50
–20
ps
ps
ps
–30
–20
–75
–50
t
jit(per)
Period jitter
(5)(2)
ps
t
jit(hper)
Half-period jitter
(5)(2)
ps
Σ
t
(su)
Σ
t
(h)
|t
jit(per)
| + |t
(
φ
)dyn
| + t
sk(o)(6)
|t
(
φ
)dyn
| + + t
sk(o)(6)
Slew rate, OE
Input clock skew rate
Output clock slew rate
(7)(8)
Output differential-pair cross voltage
(9)
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth
ps
ps
0.5
SR
1
2.5
2.5
4
3
V/ns
1.5
V
OX
(V
DDQ
/2) – 0.1
(V
DDQ
/2) + 0.1
V
30
0%
33
kHz
–0.5%
2
MHz
(1)
There are two different terminations that are used with the following tests. The load/board in
Figure 2
is used to measure the input and
output differential-pair cross voltage only. The load/board in
Figure 3
is used to measure all other tests. For consistency, equal length
cables must be used.
This parameter is assured by design and characterization.
Phase static offset time does not include jitter.
For full frequency range of 160MHz to 410MHz.
Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other.
In the frequency range of 271 MHz to 410 MHz, the minimum and maximum values of t
and t
and the maximum value for t
sk(o)
must not exceed the corresponding minimum and maximum values of the 160 MHz to 270 MHz range. In addition, the sum of the
specified values for |t
|, |t
|, and t
must meet the requirements for the
Σ
t
(su)
and the sum of the specified values for |t
(
φ
)dyn
|
and t
must meet the requirements for the
Σ
t
.
The output slew rate is determined from the IBIS model into the load shown in
Figure 4
.
To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback
clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target.
Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements
of the registered DDR2 DIMM application.
Output differential-pair cross voltage specified at the DRAM clock input or the test load.
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDCU2A877ZQLR | 功能描述:時鐘驅(qū)動器及分配 1.8V Ph-Lock Loop Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCU2A877ZQLT | 功能描述:時鐘驅(qū)動器及分配 1.8V Ph-Lock Loop Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCU877 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8V PHASE LOCK LOOP CLOCK DRIVER |
| CDCU877A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8V PHASE LOCK LOOP CLOCK DRIVER |
| CDCU877AGQL | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8V PHASE LOCK LOOP CLOCK DRIVER |
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