參數(shù)資料
型號(hào): CDCU2A877ZQL
廠商: Texas Instruments, Inc.
英文描述: 1.8-V PHASE LOCK LOOP CLOCK DRIVER
中文描述: 的1.8 V鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器
文件頁數(shù): 6/14頁
文件大?。?/td> 362K
代理商: CDCU2A877ZQL
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range
TIMING REQUIREMENTS
over recommended operating free-air temperature range
CDCU2A877
SCAS827–AUGUST 2006
AV
DD
,
V
DDG
1.7 V
1.7 V to
1.9 V
1.7 V
PARAMETERLow-level output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
IK
Input (cl inputs)
I
I
= –18 mA
I
OH
= -100
A
–1.2
V
VDDQ
– 0.2
V
OH
High-level output voltage
V
I
OH
= –18 mA
I
OL
= 100
μ
A
I
OL
= 18 mA
V
O(DL)
= 100 mV, OE = L
1.1
0.1
0.6
V
OL
Low-level output voltage
V
1.7 V
1.7 V
1.7 V
1.9 V
1.9 V
1.9 V
I
O(DL)
V
OD
Low-level output current, disabled
Differential output voltage
(1)
100
0.6
μ
A
V
CK, CK
OE, OS, FBIN, FBIN
±
250
±
10
500
I
I
Input current
μ
A
I
DD(LD)
Supply current, static (I
DDQ
+ I
ADD
)
CK and CK = L
CK and CK = 410 MHz,
All outputs are open
(not connected to a PCB)
All outputs are loaded with 2 pF
and 120-
termination resistor,
CK and CK = 410 MHz
V
I
= V
DD
or GND
V
I
= V
DD
or GND
V
I
= V
DD
or GND
V
I
= V
DD
or GND
μ
A
1.9 V
300
mA
Supply current, dynamic ( I
DDQ
+ I
ADD
) (see
(2)
for C
PD
calculation)
I
DD
1.9 V
325
mA
CK, CK
FBIN, FBIN
CK, CK
FBIN, FBIN
1.8 V
1.8 V
1.8 V
1.8 V
2
2
3
3
C
I
Input capacitance
pF
0.25
0.25
Change in input
current
C
I(
)
pF
(1)
(2)
V
is the magnitude of the difference between the true and complimentary outputs. See
Figure 4
for a definition.
Total I
= I
+ I
ADD
= f
×
C
×
V
, solving for C
= (I
DDQ
+ I
ADD
)/(f
CK
×
V
DDQ
) where f
CK
is the input frequency, V
DDQ
is the
power supply, and C
PD
is the power dissipation capacitance.
PARAMETER
TEST CONDITIONS
MIN
125
160
40%
TYP
MAX
410
410
60%
UNIT
MHz
MHz
f
CK
f
CK
t
DC
t
L
Clock frequency (operating)
(1)(2)
Clock frequency (application)
(1)(3)
Duty cycle, input clock
Stabilization time
(4)
AV
DD
, V
DD
= 1.8 V
±
0.1 V
AV
DD
, V
DD
= 1.8 V
±
0.1 V
AV
DD
, V
DD
= 1.8 V
±
0.1 V
AV
DD
, V
DD
= 1.8 V
±
0.1 V
6
μ
s
(1)
(2)
The PLL must be able to handle spread spectrum induced skew.
Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other
timing parameters (used for low speed system debug).
Application clock frequency indicates a range over which the PLL must meet all timing parameters.
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal,
within the value specified by the static phase offset t
, after power up. During normal operation, the stabilization time is also the time
required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic
low state, enter the power-down mode, and later return to active operation. CK and CK may be left floating after they have been driven
low for one complete clock cycle.
(3)
(4)
6
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