參數(shù)資料
型號: CDCU2A877ZQL
廠商: Texas Instruments, Inc.
英文描述: 1.8-V PHASE LOCK LOOP CLOCK DRIVER
中文描述: 的1.8 V鎖相環(huán)時鐘驅(qū)動器
文件頁數(shù): 4/14頁
文件大?。?/td> 362K
代理商: CDCU2A877ZQL
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
CDCU2A877
SCAS827–AUGUST 2006
Figure 1. Logic Diagram (Positive Logic)
VALUE
UNIT
V
DDQ
A
VDD
V
I
V
O
I
IK
I
OK
I
O
I
DDC
Supply voltage range
–0.5 tp 2.5
V
Input voltage range
(2)(3)
Output voltage range
(2)(3)
Input clamp current, (V
I
< 0 or V
I
> V
DDQ
)
Output clamp voltage, (V
O
< 0 or V
O
> V
DDQ
)
Continuous output current, (V
O
= 0 to V
DDQ
)
Continuous current through each V
DDQ
or GND
–0.5 to V
DDQ
+ 0.5
–0.5 to V
DDQ
+ 0.5
±
50
±
50
±
50
±
100
151.9
146.1
102.4
–65 to 150
V
V
mA
mA
mA
mA
No airflow
Airllflow 150 ft/min
No airflow
R
θ
JA
Thermal resistance, junction-to-ambient
(4)
K/W
R
θ
JC
T
stg
Thermal resistance, junction-to-case
(4)
Storage temperature range
°
C
(1)
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 2.5 V maximum.
The package thermal impedance is calculated in accordance with JESD51 and JEDEC2S1P (high-k board).
(2)
(3)
(4)
4
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