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參數(shù)資料
| 型號： | CDCL6010_07 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer |
| 中文描述： | 1.8伏，11輸出時鐘倍頻，分銷商，抖動清除器和緩沖器 |
| 文件頁數(shù)： | 2/27頁 |
| 文件大小： | 571K |
| 代理商： | CDCL6010_07 |
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DESCRIPTION
The CDCL6010 is a high-performance, low phase
noise clock multiplier, distributor, jitter cleaner, and
low skew buffer. It effectively cleans a noisy system
clock with a fully-integrated low noise Voltage
Controlled Oscillator (VCO) that operates in the
1.2GHz–1.275GHz
range.
oscillator oscillates in the 2.4GHz–2.55GHz range.
The
frequency
is
predivided
post-dividers P0 and P1.)
CDCL6010
SLLS780–FEBRUARY 2007
The CDCL6010 supports one differential LVDS clock
input and a total of 11 differential CML outputs. One
output is a straight bypass with no support for jitter
cleaning or clock multiplication. The remaining 10
outputs are available in two groups of five outputs
each with independent frequency division ratios.
Those 10 outputs can be optionally setup to bypass
the PLL when no jitter cleaning is needed. The CML
outputs are compatible with LVDS receivers if
ac-coupled.
(Note
that
the
LC
by
2
before
the
The output frequency (F
OUT
) is synchronized to the
frequency of the input clock (F
). The programmable
pre-dividers, M and N, and the post-dividers, P0 and
P1, give a high flexibility to the ratio of the output
frequency to the input frequency:
F
OUT
= F
IN
×
N/(M
×
P)
Where:
P (P0, P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80
M = 1, 2, 4, 8
N = 32, 40
With careful observation of the input voltage swing
and common-mode voltage limits, the CDCL6010
can support a single-ended clock input as outlined in
the Pin Description Table
.
The CDCL6010 can operate as a multi-output clock
buffer in a PLL bypass mode.
All device settings are programmable through the
SDA/SCL, serial two-wire interface.
The phase of one output group relative to the other
can be adjusted through the SDA/SCL interface. For
post-divide ratios (P0, P1) that are multiples of 5, the
total number of phase adjustment steps (
n
) equals
the divide-ratio divided by 5. For post-divide ratios
(P0, P1) that are not multiples of 5, the total number
of steps (
n
) is the same as the post-divide ratio. The
phase adjustment step (
Φ
) in time units is given as:
Φ
= 1/(n
×
F
OUT
)
where F
OUT
is the respective output frequency.
The device operates in a 1.8V supply environment
and is characterized for operation from –40
°
C to
+85
°
C.
The CDCL6010 is available in a 48-pin QFN (RGZ)
package.
provided that:
30MHz < (F
IN
/M) < 40MHz
1200MHz < (F
OUT
×
P) < 1275MHz
The PLL loop bandwidth is user-selectable by
external filter components or by using the internal
loop filter. The PLL loop bandwidth and damping
factor can be adjusted to meet different system
requirements.
2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDCL6010RGZR | 功能描述:時鐘合成器/抖動清除器 11Outputs Clock Mult Dist Cleaner Buffer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCL6010RGZRG4 | 功能描述:時鐘合成器/抖動清除器 1.8V 11-Output Clock Mult Distr Jitter RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCL6010RGZT | 功能描述:時鐘合成器/抖動清除器 11Outputs Clock Mult Dist Cleaner Buffer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCL6010RGZTG4 | 功能描述:時鐘合成器/抖動清除器 1.8V 11-Output Clock Mult Distr Jitter RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDCLP2 | 制造商:Panduit Corp 功能描述:CORNER WIRING DUCT CLIP |
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